forked from OSchip/llvm-project
IRgen/ABI/ARM: Return large vectors in memory.
llvm-svn: 114619
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@ -2391,6 +2391,10 @@ ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy) const {
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if (RetTy->isVoidType())
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return ABIArgInfo::getIgnore();
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// Large vector types should be returned via memory.
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if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
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return ABIArgInfo::getIndirect(0);
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if (!isAggregateTypeForABI(RetTy)) {
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// Treat an enum type as its underlying type.
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if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
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@ -11,3 +11,19 @@
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int8x16_t f0(int8x16_t a0, int8x16_t a1) {
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return vzipq_s8(a0, a1).val[0];
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}
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// Test direct vector passing.
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typedef float T_float32x2 __attribute__ ((__vector_size__ (8)));
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typedef float T_float32x4 __attribute__ ((__vector_size__ (16)));
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typedef float T_float32x8 __attribute__ ((__vector_size__ (32)));
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typedef float T_float32x16 __attribute__ ((__vector_size__ (64)));
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// CHECK: define <2 x float> @f1_0(<2 x float> %{{.*}})
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T_float32x2 f1_0(T_float32x2 a0) { return a0; }
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// CHECK: define <4 x float> @f1_1(<4 x float> %{{.*}})
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T_float32x4 f1_1(T_float32x4 a0) { return a0; }
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// CHECK: define void @f1_2(<8 x float>* sret %{{.*}}, <8 x float> %{{.*}})
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T_float32x8 f1_2(T_float32x8 a0) { return a0; }
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// CHECK: define void @f1_3(<16 x float>* sret %{{.*}}, <16 x float> %{{.*}})
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T_float32x16 f1_3(T_float32x16 a0) { return a0; }
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