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Add BTVER2 sched support for SHLD/SHRD. 

Differential Revision: https://reviews.llvm.org/D40124

llvm-svn: 318977
This commit is contained in:
Andrew V. Tischenko 2017-11-25 10:46:53 +00:00
parent c160cfaf66
commit 198720d38e
2 changed files with 48 additions and 24 deletions
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24
llvm/lib/Target/X86/X86ScheduleBtVer2.td
View File

@ -135,6 +135,30 @@ def : WriteRes<WriteLEA, [JALU01]>;
defm : JWriteResIntPair<WriteShift, JALU01, 1>;
def WriteSHLDrri : SchedWriteRes<[JALU01]> {
let Latency = 3;
let ResourceCycles = [6];
let NumMicroOps = 6;
}
def: InstRW<[WriteSHLDrri], (instregex "SHLD(16|32|64)rri8")>;
def: InstRW<[WriteSHLDrri], (instregex "SHRD(16|32|64)rri8")>;
def WriteSHLDrrCL : SchedWriteRes<[JALU01]> {
let Latency = 4;
let ResourceCycles = [8];
let NumMicroOps = 7;
}
def: InstRW<[WriteSHLDrrCL], (instregex "SHLD(16|32|64)rrCL")>;
def: InstRW<[WriteSHLDrrCL], (instregex "SHRD(16|32|64)rrCL")>;
def WriteSHLDm : SchedWriteRes<[JLAGU, JALU01]> {
let Latency = 9;
let ResourceCycles = [1, 22];
let NumMicroOps = 8;
}
def: InstRW<[WriteSHLDm], (instregex "SHLD(16|32|64)mr(i8|CL)")>;
def: InstRW<[WriteSHLDm], (instregex "SHRD(16|32|64)mr(i8|CL)")>;
////////////////////////////////////////////////////////////////////////////////
// Loads, stores, and moves, not folded with other operations.
// FIXME: Split x86 and SSE load/store/moves

48
llvm/test/CodeGen/X86/schedule-x86_64.ll
View File

@ -1291,14 +1291,14 @@ define void @test_shld_shrd_16(i16 %a0, i16 %a1, i16 *%a2) optsize {
; BTVER2-LABEL: test_shld_shrd_16:
; BTVER2: # BB#0:
; BTVER2-NEXT: #APP
; BTVER2-NEXT: shldw %cl, %si, %di # sched: [1:0.50]
; BTVER2-NEXT: shrdw %cl, %si, %di # sched: [1:0.50]
; BTVER2-NEXT: shldw %cl, %si, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shrdw %cl, %si, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shldw $7, %si, %di # sched: [1:0.50]
; BTVER2-NEXT: shrdw $7, %si, %di # sched: [1:0.50]
; BTVER2-NEXT: shldw $7, %si, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shrdw $7, %si, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shldw %cl, %si, %di # sched: [4:4.00]
; BTVER2-NEXT: shrdw %cl, %si, %di # sched: [4:4.00]
; BTVER2-NEXT: shldw %cl, %si, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: shrdw %cl, %si, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: shldw $7, %si, %di # sched: [3:3.00]
; BTVER2-NEXT: shrdw $7, %si, %di # sched: [3:3.00]
; BTVER2-NEXT: shldw $7, %si, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: shrdw $7, %si, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@ -1434,14 +1434,14 @@ define void @test_shld_shrd_32(i32 %a0, i32 %a1, i32 *%a2) optsize {
; BTVER2-LABEL: test_shld_shrd_32:
; BTVER2: # BB#0:
; BTVER2-NEXT: #APP
; BTVER2-NEXT: shldl %cl, %esi, %edi # sched: [1:0.50]
; BTVER2-NEXT: shrdl %cl, %esi, %edi # sched: [1:0.50]
; BTVER2-NEXT: shldl %cl, %esi, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shrdl %cl, %esi, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shldl $7, %esi, %edi # sched: [1:0.50]
; BTVER2-NEXT: shrdl $7, %esi, %edi # sched: [1:0.50]
; BTVER2-NEXT: shldl $7, %esi, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shrdl $7, %esi, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shldl %cl, %esi, %edi # sched: [4:4.00]
; BTVER2-NEXT: shrdl %cl, %esi, %edi # sched: [4:4.00]
; BTVER2-NEXT: shldl %cl, %esi, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: shrdl %cl, %esi, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: shldl $7, %esi, %edi # sched: [3:3.00]
; BTVER2-NEXT: shrdl $7, %esi, %edi # sched: [3:3.00]
; BTVER2-NEXT: shldl $7, %esi, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: shrdl $7, %esi, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retq # sched: [4:1.00]
;
@ -1577,14 +1577,14 @@ define void @test_shld_shrd_64(i64 %a0, i64 %a1, i64 *%a2) optsize {
; BTVER2-LABEL: test_shld_shrd_64:
; BTVER2: # BB#0:
; BTVER2-NEXT: #APP
; BTVER2-NEXT: shldq %cl, %rsi, %rdi # sched: [1:0.50]
; BTVER2-NEXT: shrdq %cl, %rsi, %rdi # sched: [1:0.50]
; BTVER2-NEXT: shldq %cl, %rsi, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shrdq %cl, %rsi, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shldq $7, %rsi, %rdi # sched: [1:0.50]
; BTVER2-NEXT: shrdq $7, %rsi, %rdi # sched: [1:0.50]
; BTVER2-NEXT: shldq $7, %rsi, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shrdq $7, %rsi, (%rdx) # sched: [4:1.00]
; BTVER2-NEXT: shldq %cl, %rsi, %rdi # sched: [4:4.00]
; BTVER2-NEXT: shrdq %cl, %rsi, %rdi # sched: [4:4.00]
; BTVER2-NEXT: shldq %cl, %rsi, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: shrdq %cl, %rsi, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: shldq $7, %rsi, %rdi # sched: [3:3.00]
; BTVER2-NEXT: shrdq $7, %rsi, %rdi # sched: [3:3.00]
; BTVER2-NEXT: shldq $7, %rsi, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: shrdq $7, %rsi, (%rdx) # sched: [9:11.00]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retq # sched: [4:1.00]
;