diff --git a/llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll b/llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll
index 3d82fe53e6e8..1ab013835737 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll
@@ -16,6 +16,19 @@ define i32 @anyset_two_bit_mask(i32 %x) {
   ret i32 %r
 }
 
+define <2 x i32> @anyset_two_bit_mask_uniform(<2 x i32> %x) {
+; CHECK-LABEL: @anyset_two_bit_mask_uniform(
+; CHECK-NEXT:    [[S:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 3, i32 3>
+; CHECK-NEXT:    [[O:%.*]] = or <2 x i32> [[S]], [[X]]
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i32> [[O]], <i32 1, i32 1>
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %s = lshr <2 x i32> %x, <i32 3, i32 3>
+  %o = or <2 x i32> %s, %x
+  %r = and <2 x i32> %o, <i32 1, i32 1>
+  ret <2 x i32> %r
+}
+
 define i32 @anyset_four_bit_mask(i32 %x) {
 ; CHECK-LABEL: @anyset_four_bit_mask(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 297
@@ -33,6 +46,27 @@ define i32 @anyset_four_bit_mask(i32 %x) {
   ret i32 %r
 }
 
+define <2 x i32> @anyset_four_bit_mask_uniform(<2 x i32> %x) {
+; CHECK-LABEL: @anyset_four_bit_mask_uniform(
+; CHECK-NEXT:    [[T1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 3, i32 3>
+; CHECK-NEXT:    [[T2:%.*]] = lshr <2 x i32> [[X]], <i32 5, i32 5>
+; CHECK-NEXT:    [[T3:%.*]] = lshr <2 x i32> [[X]], <i32 8, i32 8>
+; CHECK-NEXT:    [[O1:%.*]] = or <2 x i32> [[T1]], [[X]]
+; CHECK-NEXT:    [[O2:%.*]] = or <2 x i32> [[T2]], [[T3]]
+; CHECK-NEXT:    [[O3:%.*]] = or <2 x i32> [[O1]], [[O2]]
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i32> [[O3]], <i32 1, i32 1>
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %t1 = lshr <2 x i32> %x, <i32 3, i32 3>
+  %t2 = lshr <2 x i32> %x, <i32 5, i32 5>
+  %t3 = lshr <2 x i32> %x, <i32 8, i32 8>
+  %o1 = or <2 x i32> %t1, %x
+  %o2 = or <2 x i32> %t2, %t3
+  %o3 = or <2 x i32> %o1, %o2
+  %r = and <2 x i32> %o3, <i32 1, i32 1>
+  ret <2 x i32> %r
+}
+
 ; We're not testing the LSB here, so all of the 'or' operands are shifts.
 
 define i32 @anyset_three_bit_mask_all_shifted_bits(i32 %x) {
@@ -51,6 +85,25 @@ define i32 @anyset_three_bit_mask_all_shifted_bits(i32 %x) {
   ret i32 %r
 }
 
+define <2 x i32> @anyset_three_bit_mask_all_shifted_bits_uniform(<2 x i32> %x) {
+; CHECK-LABEL: @anyset_three_bit_mask_all_shifted_bits_uniform(
+; CHECK-NEXT:    [[T1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 3, i32 3>
+; CHECK-NEXT:    [[T2:%.*]] = lshr <2 x i32> [[X]], <i32 5, i32 5>
+; CHECK-NEXT:    [[T3:%.*]] = lshr <2 x i32> [[X]], <i32 8, i32 8>
+; CHECK-NEXT:    [[O2:%.*]] = or <2 x i32> [[T2]], [[T3]]
+; CHECK-NEXT:    [[O3:%.*]] = or <2 x i32> [[T1]], [[O2]]
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i32> [[O3]], <i32 1, i32 1>
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %t1 = lshr <2 x i32> %x, <i32 3, i32 3>
+  %t2 = lshr <2 x i32> %x, <i32 5, i32 5>
+  %t3 = lshr <2 x i32> %x, <i32 8, i32 8>
+  %o2 = or <2 x i32> %t2, %t3
+  %o3 = or <2 x i32> %t1, %o2
+  %r = and <2 x i32> %o3, <i32 1, i32 1>
+  ret <2 x i32> %r
+}
+
 ; Recognize the 'and' sibling pattern (all-bits-set). The 'and 1' may not be at the end.
 
 define i32 @allset_two_bit_mask(i32 %x) {
@@ -66,6 +119,19 @@ define i32 @allset_two_bit_mask(i32 %x) {
   ret i32 %r
 }
 
+define <2 x i32> @allset_two_bit_mask_uniform(<2 x i32> %x) {
+; CHECK-LABEL: @allset_two_bit_mask_uniform(
+; CHECK-NEXT:    [[S:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 7, i32 7>
+; CHECK-NEXT:    [[O:%.*]] = and <2 x i32> [[S]], [[X]]
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i32> [[O]], <i32 1, i32 1>
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %s = lshr <2 x i32> %x, <i32 7, i32 7>
+  %o = and <2 x i32> %s, %x
+  %r = and <2 x i32> %o, <i32 1, i32 1>
+  ret <2 x i32> %r
+}
+
 define i64 @allset_four_bit_mask(i64 %x) {
 ; CHECK-LABEL: @allset_four_bit_mask(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i64 [[X:%.*]], 30