diff --git a/llvm/include/llvm/Target/TargetInstrInfo.h b/llvm/include/llvm/Target/TargetInstrInfo.h
index cf1d11a9377a..bc25fa722b7d 100644
--- a/llvm/include/llvm/Target/TargetInstrInfo.h
+++ b/llvm/include/llvm/Target/TargetInstrInfo.h
@@ -51,7 +51,6 @@ const unsigned M_BARRIER_FLAG           = 1 << 4;
 const unsigned M_CC_FLAG		= 1 << 6;
 const unsigned M_LOAD_FLAG		= 1 << 10;
 const unsigned M_STORE_FLAG		= 1 << 12;
-const unsigned M_DUMMY_PHI_FLAG	= 1 << 13;
 // 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
 const unsigned M_2_ADDR_FLAG           = 1 << 15;
 
@@ -203,10 +202,6 @@ public:
   bool isStore(MachineOpCode Opcode) const {
     return get(Opcode).Flags & M_STORE_FLAG;
   }
-  bool isDummyPhiInstr(MachineOpCode Opcode) const {
-    return get(Opcode).Flags & M_DUMMY_PHI_FLAG;
-  }
-
   virtual bool hasResultInterlock(MachineOpCode Opcode) const {
     return true;
   }
diff --git a/llvm/lib/Target/SparcV9/SparcV9Instr.def b/llvm/lib/Target/SparcV9/SparcV9Instr.def
index b0f550287a8c..53d24a596a44 100644
--- a/llvm/lib/Target/SparcV9/SparcV9Instr.def
+++ b/llvm/lib/Target/SparcV9/SparcV9Instr.def
@@ -530,8 +530,7 @@ I(WRCCRi,  "wr",         3,   2, 0, false,  0,  1,  SPARC_SINGLE,   M_CC_FLAG)
 
 // Synthetic phi operation for near-SSA form of machine code
 // Number of operands is variable, indicated by -1.  Result is the first op.
-I(PHI, "<phi>", 	-1, 0,   0, false, 0, 0,  SPARC_NONE,  M_DUMMY_PHI_FLAG)
-
+I(PHI, "<phi>", 	-1, 0,   0, false, 0, 0,  SPARC_NONE,  0)
 
 #undef B5
 #undef B6