forked from OSchip/llvm-project
parent
09455d94bf
commit
1933f20aa4
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@ -38,9 +38,8 @@ const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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/// any side effects other than loading from the stack slot.
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unsigned MipsSEInstrInfo::
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unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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int &FrameIndex) const {
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{
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unsigned Opc = MI->getOpcode();
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
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if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
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@ -61,9 +60,8 @@ isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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/// any side effects other than storing to the stack slot.
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unsigned MipsSEInstrInfo::
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unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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int &FrameIndex) const {
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{
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unsigned Opc = MI->getOpcode();
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unsigned Opc = MI->getOpcode();
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if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
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if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
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