forked from OSchip/llvm-project
parent
09455d94bf
commit
1933f20aa4
|
@ -38,9 +38,8 @@ const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
|
|||
/// the destination along with the FrameIndex of the loaded stack slot. If
|
||||
/// not, return 0. This predicate must return 0 if the instruction has
|
||||
/// any side effects other than loading from the stack slot.
|
||||
unsigned MipsSEInstrInfo::
|
||||
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
{
|
||||
unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
||||
int &FrameIndex) const {
|
||||
unsigned Opc = MI->getOpcode();
|
||||
|
||||
if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
|
||||
|
@ -61,9 +60,8 @@ isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
|||
/// the source reg along with the FrameIndex of the loaded stack slot. If
|
||||
/// not, return 0. This predicate must return 0 if the instruction has
|
||||
/// any side effects other than storing to the stack slot.
|
||||
unsigned MipsSEInstrInfo::
|
||||
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
{
|
||||
unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
|
||||
int &FrameIndex) const {
|
||||
unsigned Opc = MI->getOpcode();
|
||||
|
||||
if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
|
||||
|
|
Loading…
Reference in New Issue