From 190f3fbba8f0fad9bd3c566a69396ddfe1674a2c Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
Date: Wed, 27 Jul 2022 11:17:54 -0700
Subject: [PATCH] [AMDGPU] Precommit s_setprio scheduling test. NFC.

---
 llvm/test/CodeGen/AMDGPU/sched-setprio.ll | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/sched-setprio.ll

diff --git a/llvm/test/CodeGen/AMDGPU/sched-setprio.ll b/llvm/test/CodeGen/AMDGPU/sched-setprio.ll
new file mode 100644
index 000000000000..06885dc28eda
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/sched-setprio.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
+
+declare void @llvm.amdgcn.s.setprio(i16)
+declare <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float, float, <4 x float>, i32, i32, i32)
+
+; FIXME: setprio shall surround mfma instructions
+
+; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32:
+; GCN: s_setprio 1
+; GCN: s_setprio 0
+; GCN: v_mfma
+; GCN: v_mfma
+define amdgpu_kernel void @test_mfma_f32_4x4x1f32(<4 x float> addrspace(1)* %arg) #0 {
+bb:
+  %in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg
+  call void @llvm.amdgcn.s.setprio(i16 1)
+  %mai.1 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 1.0, float 2.0, <4 x float> %in.1, i32 0, i32 0, i32 0)
+  %mai.2 = tail call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float 3.0, float 4.0, <4 x float> %mai.1, i32 0, i32 0, i32 0)
+  call void @llvm.amdgcn.s.setprio(i16 0)
+  store <4 x float> %mai.2, <4 x float> addrspace(1)* %arg
+  ret void
+}