forked from OSchip/llvm-project
Make ppc64 jit kinda work right. About 2/3 of Olden passes with this,
there are clearly some encoding bugs lurking in there somewhere. llvm-svn: 29949
This commit is contained in:
Nate Begeman
parent
0b4e05a28c
commit
18f0329cfc
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@ -27,32 +27,50 @@ static TargetJITInfo::JITCompilerFn JITCompilerFunction;
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((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
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#define BUILD_ORI(RD,RS,UIMM16) \
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((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
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#define BUILD_ORIS(RD,RS,UIMM16) \
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((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
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#define BUILD_RLDICR(RD,RS,SH,ME) \
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((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
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(((ME) & 63) << 6) | (1 << 3) | (((SH) >> 5) & 1))
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#define BUILD_MTSPR(RS,SPR) \
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((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
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#define BUILD_BCCTRx(BO,BI,LINK) \
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((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1))
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#define BUILD_B(TARGET, LINK) \
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((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1))
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// Pseudo-ops
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#define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16)
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#define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
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#define BUILD_MTCTR(RS) BUILD_MTSPR(RS,9)
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#define BUILD_BCTR(LINK) BUILD_BCCTRx(20,0,LINK)
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static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){
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intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2;
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unsigned *AtI = (unsigned*)(intptr_t)At;
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static void EmitBranchToAt(void *At, void *To, bool isCall) {
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intptr_t Addr = (intptr_t)To;
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// FIXME: should special case the short branch case.
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unsigned *AtI = (unsigned*)At;
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AtI[0] = BUILD_LIS(12, Addr >> 16); // lis r12, hi16(address)
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AtI[1] = BUILD_ORI(12, 12, Addr); // ori r12, r12, low16(address)
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AtI[2] = BUILD_MTCTR(12); // mtctr r12
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AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl
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if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range?
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AtI[0] = BUILD_B(Offset, isCall); // b/bl target
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} else if (!is64Bit) {
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AtI[0] = BUILD_LIS(12, To >> 16); // lis r12, hi16(address)
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AtI[1] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
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AtI[2] = BUILD_MTCTR(12); // mtctr r12
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AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl
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} else {
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AtI[0] = BUILD_LIS(12, To >> 48); // lis r12, hi16(address)
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AtI[1] = BUILD_ORI(12, 12, To >> 32); // ori r12, r12, lo16(address)
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AtI[2] = BUILD_SLDI(12, 12, 32); // sldi r12, r12, 32
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AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
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AtI[4] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address)
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AtI[5] = BUILD_MTCTR(12); // mtctr r12
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AtI[6] = BUILD_BCTR(isCall); // bctr/bctrl
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}
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}
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extern "C" void PPC32CompilationCallback();
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extern "C" void PPC64CompilationCallback();
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#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
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#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && !defined(__ppc64__)
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// CompilationCallback stub - We can't use a C function with inline assembly in
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// it, because we the prolog/epilog inserted by GCC won't work for us. Instead,
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// write our own wrapper, which does things our way, so we have complete control
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@ -64,6 +82,7 @@ asm(
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"_PPC32CompilationCallback:\n"
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// Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
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// FIXME: need to save v[0-19] for altivec?
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// FIXME: could shrink frame
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// Set up a proper stack frame
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"stwu r1, -208(r1)\n"
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"mflr r0\n"
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@ -87,7 +106,8 @@ asm(
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"mr r3, r0\n"
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"lwz r2, 208(r1)\n" // stub's frame
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"lwz r4, 8(r2)\n" // stub's lr
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"bl _PPC32CompilationCallbackC\n"
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"li r5, 0\n" // 0 == 32 bit
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"bl _PPCCompilationCallbackC\n"
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"mtctr r3\n"
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// Restore all int arg registers
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"lwz r10, 204(r1)\n" "lwz r9, 200(r1)\n"
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@ -115,8 +135,69 @@ void PPC32CompilationCallback() {
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}
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#endif
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extern "C" unsigned *PPC32CompilationCallbackC(unsigned *StubCallAddrPlus4,
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unsigned *OrigCallAddrPlus4) {
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#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && defined(__ppc64__)
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asm(
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".text\n"
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".align 2\n"
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".globl _PPC64CompilationCallback\n"
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"_PPC64CompilationCallback:\n"
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// Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the
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// FIXME: need to save v[0-19] for altivec?
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// Set up a proper stack frame
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"stdu r1, -208(r1)\n"
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"mflr r0\n"
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"std r0, 224(r1)\n"
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// Save all int arg registers
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"std r10, 200(r1)\n" "std r9, 192(r1)\n"
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"std r8, 184(r1)\n" "std r7, 176(r1)\n"
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"std r6, 168(r1)\n" "std r5, 160(r1)\n"
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"std r4, 152(r1)\n" "std r3, 144(r1)\n"
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// Save all call-clobbered FP regs.
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"stfd f13, 136(r1)\n" "stfd f12, 128(r1)\n"
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"stfd f11, 120(r1)\n" "stfd f10, 112(r1)\n"
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"stfd f9, 104(r1)\n" "stfd f8, 96(r1)\n"
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"stfd f7, 88(r1)\n" "stfd f6, 80(r1)\n"
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"stfd f5, 72(r1)\n" "stfd f4, 64(r1)\n"
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"stfd f3, 56(r1)\n" "stfd f2, 48(r1)\n"
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"stfd f1, 40(r1)\n"
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// Arguments to Compilation Callback:
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// r3 - our lr (address of the call instruction in stub plus 4)
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// r4 - stub's lr (address of instruction that called the stub plus 4)
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"mr r3, r0\n"
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"ld r2, 208(r1)\n" // stub's frame
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"ld r4, 16(r2)\n" // stub's lr
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"li r5, 1\n" // 1 == 64 bit
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"bl _PPCCompilationCallbackC\n"
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"mtctr r3\n"
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// Restore all int arg registers
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"ld r10, 200(r1)\n" "ld r9, 192(r1)\n"
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"ld r8, 184(r1)\n" "ld r7, 176(r1)\n"
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"ld r6, 168(r1)\n" "ld r5, 160(r1)\n"
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"ld r4, 152(r1)\n" "ld r3, 144(r1)\n"
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// Restore all FP arg registers
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"lfd f13, 136(r1)\n" "lfd f12, 128(r1)\n"
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"lfd f11, 120(r1)\n" "lfd f10, 112(r1)\n"
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"lfd f9, 104(r1)\n" "lfd f8, 96(r1)\n"
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"lfd f7, 88(r1)\n" "lfd f6, 80(r1)\n"
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"lfd f5, 72(r1)\n" "lfd f4, 64(r1)\n"
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"lfd f3, 56(r1)\n" "lfd f2, 48(r1)\n"
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"lfd f1, 40(r1)\n"
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// Pop 3 frames off the stack and branch to target
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"ld r1, 208(r1)\n"
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"ld r2, 16(r1)\n"
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"mtlr r2\n"
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"bctr\n"
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);
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#else
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void PPC64CompilationCallback() {
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assert(0 && "This is not a power pc, you can't execute this!");
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abort();
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}
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#endif
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extern "C" void *PPCCompilationCallbackC(unsigned *StubCallAddrPlus4,
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unsigned *OrigCallAddrPlus4,
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bool is64Bit) {
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// Adjust the pointer to the address of the call instruction in the stub
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// emitted by emitFunctionStub, rather than the instruction after it.
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unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
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@ -143,17 +224,21 @@ extern "C" unsigned *PPC32CompilationCallbackC(unsigned *StubCallAddrPlus4,
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// Assert that we are coming from a stub that was created with our
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// emitFunctionStub.
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if ((*StubCallAddr >> 26) == 18)
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StubCallAddr -= 3;
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else {
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assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!");
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StubCallAddr -= 6;
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StubCallAddr -= is64Bit ? 9 : 6;
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}
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// Rewrite the stub with an unconditional branch to the target, for any users
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// who took the address of the stub.
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EmitBranchToAt(StubCallAddr, Target, false);
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EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit);
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// Put the address of the target function to call and the address to return to
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// after calling the target function in a place that is easy to get on the
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// stack after we restore all regs.
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return (unsigned *)Target;
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return Target;
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}
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@ -161,33 +246,46 @@ extern "C" unsigned *PPC32CompilationCallbackC(unsigned *StubCallAddrPlus4,
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TargetJITInfo::LazyResolverFn
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PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
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JITCompilerFunction = Fn;
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return PPC32CompilationCallback;
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return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback;
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}
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void *PPCJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
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// If this is just a call to an external function, emit a branch instead of a
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// call. The code is the same except for one bit of the last instruction.
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if (Fn != (void*)(intptr_t)PPC32CompilationCallback) {
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MCE.startFunctionStub(4*4);
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void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue();
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if (Fn != (void*)(intptr_t)PPC32CompilationCallback &&
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Fn != (void*)(intptr_t)PPC64CompilationCallback) {
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MCE.startFunctionStub(7*4);
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intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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EmitBranchToAt(Addr, Fn, false);
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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EmitBranchToAt(Addr, (intptr_t)Fn, false, is64Bit);
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return MCE.finishFunctionStub(0);
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}
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MCE.startFunctionStub(4*7);
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MCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1)
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MCE.emitWordBE(0x7d6802a6); // mflr r11
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MCE.emitWordBE(0x91610028); // stw r11, 40(r1)
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void *Addr = (void*)(intptr_t)MCE.getCurrentPCValue();
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MCE.startFunctionStub(10*4);
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if (is64Bit) {
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MCE.emitWordBE(0xf821ffb1); // stdu r1,-80(r1)
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MCE.emitWordBE(0x7d6802a6); // mflr r11
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MCE.emitWordBE(0xf9610060); // std r11, 96(r1)
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} else {
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MCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1)
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MCE.emitWordBE(0x7d6802a6); // mflr r11
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MCE.emitWordBE(0x91610028); // stw r11, 40(r1)
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}
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intptr_t Addr = (intptr_t)MCE.getCurrentPCValue();
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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EmitBranchToAt(Addr, Fn, true/*is call*/);
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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MCE.emitWordBE(0);
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EmitBranchToAt(Addr, (intptr_t)Fn, true, is64Bit);
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return MCE.finishFunctionStub(0);
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}
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@ -251,5 +349,5 @@ void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
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}
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void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
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EmitBranchToAt(Old, New, false);
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EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit);
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}
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@ -22,8 +22,12 @@ namespace llvm {
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class PPCJITInfo : public TargetJITInfo {
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protected:
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PPCTargetMachine &TM;
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bool is64Bit;
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public:
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PPCJITInfo(PPCTargetMachine &tm) : TM(tm) {useGOT = 0;}
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PPCJITInfo(PPCTargetMachine &tm, bool tmIs64Bit) : TM(tm) {
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useGOT = 0;
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is64Bit = tmIs64Bit;
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target. Return true if this
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@ -87,7 +87,7 @@ PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS,
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bool is64Bit)
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: TargetMachine("PowerPC"), Subtarget(M, FS, is64Bit),
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DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
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FrameInfo(*this, false), JITInfo(*this), TLInfo(*this),
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FrameInfo(*this, false), JITInfo(*this, is64Bit), TLInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()) {
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if (getRelocationModel() == Reloc::Default)
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