forked from OSchip/llvm-project
[M68k] Adopt VarLenCodeEmitter for move instructions
The `move` instruction has one of the most complicate sets of variants, so we're refactoring it first before finishing up rest of the data instructions in a separate patch. Note that since we're introducing more `move` variants, the codegen actually got improved in terms of code size.
This commit is contained in:
Min-Yih Hsu
parent
f927106e10
commit
18b38ff6c7
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@ -42,290 +42,176 @@
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/// -----------------------------------------------------
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///
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/// NOTE Move requires EA X version for direct register destination(0)
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class MxMoveEncoding<MxBead2Bits size,
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MxEncEA srcEA, MxEncExt srcExt,
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MxEncEA dstEA, MxEncExt dstExt>
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: MxEncoding<srcEA.Reg, srcEA.DA, srcEA.Mode, dstEA.DA, dstEA.Mode, dstEA.Reg,
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size, MxBead2Bits<0b00>,
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srcExt.Imm, srcExt.B8, srcExt.Scale, srcExt.WL, srcExt.DAReg,
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dstExt.Imm, dstExt.B8, dstExt.Scale, dstExt.WL, dstExt.DAReg>;
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/// MOVE has alternate size encoding
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class MxMoveSize<bits<2> value> : MxBead2Bits<value>;
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// MOVE has a different size encoding.
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class MxMoveSize<bits<2> value> {
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bits<2> Value = value;
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}
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def MxMoveSize8 : MxMoveSize<0b01>;
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def MxMoveSize16 : MxMoveSize<0b11>;
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def MxMoveSize32 : MxMoveSize<0b10>;
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let Defs = [CCR] in
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class MxMove<string size, dag outs, dag ins, list<dag> pattern, MxEncoding enc>
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: MxInst<outs, ins, "move."#size#"\t$src, $dst", pattern, enc>;
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class MxMoveEncoding<MxMoveSize size, MxEncMemOp dst_enc, MxEncMemOp src_enc> {
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dag Value = (ascend
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(descend 0b00, size.Value,
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!cond(
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!eq(!getdagop(dst_enc.EA), descend): !setdagop(dst_enc.EA, ascend),
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!eq(!getdagop(dst_enc.EA), ascend): !setdagop(dst_enc.EA, descend)),
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src_enc.EA),
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// Source extension
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src_enc.Supplement,
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// Destination extension
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dst_enc.Supplement
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);
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}
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class MxMove_RR<MxType DST, MxType SRC, MxMoveEncoding ENC>
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: MxMove<DST.Prefix, (outs DST.ROp:$dst), (ins SRC.ROp:$src),
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// Special encoding for Xn
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class MxMoveEncAddrMode_r<string reg_opnd> : MxEncMemOp {
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let EA = (descend (descend 0b00, (slice "$"#reg_opnd, 3, 3)),
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(operand "$"#reg_opnd, 3));
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}
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multiclass MxMoveOperandEncodings<string opnd_name> {
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// Dn
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def MxMove#NAME#OpEnc_d : MxEncAddrMode_d<opnd_name>;
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// An
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def MxMove#NAME#OpEnc_a : MxEncAddrMode_a<opnd_name>;
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// Xn
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def MxMove#NAME#OpEnc_r : MxMoveEncAddrMode_r<opnd_name>;
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// (An)+
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def MxMove#NAME#OpEnc_o : MxEncAddrMode_o<opnd_name>;
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// -(An)
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def MxMove#NAME#OpEnc_e : MxEncAddrMode_e<opnd_name>;
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// (i,PC,Xn)
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def MxMove#NAME#OpEnc_k : MxEncAddrMode_k<opnd_name>;
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// (i,PC)
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def MxMove#NAME#OpEnc_q : MxEncAddrMode_q<opnd_name>;
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// (i,An,Xn)
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def MxMove#NAME#OpEnc_f : MxEncAddrMode_f<opnd_name>;
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// (i,An)
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def MxMove#NAME#OpEnc_p : MxEncAddrMode_p<opnd_name>;
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// (ABS).L
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def MxMove#NAME#OpEnc_b : MxEncAddrMode_abs<opnd_name, /*W/L=*/true>;
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// (An)
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def MxMove#NAME#OpEnc_j : MxEncAddrMode_j<opnd_name>;
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}
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defm Src : MxMoveOperandEncodings<"src">;
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defm Dst : MxMoveOperandEncodings<"dst">;
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defvar MxMoveSupportedAMs = ["o", "e", "k", "q", "f", "p", "b", "j"];
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let Defs = [CCR] in
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class MxMove<string size, dag outs, dag ins, list<dag> pattern, MxMoveEncoding enc>
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: MxInst<outs, ins, "move."#size#"\t$src, $dst", pattern> {
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let Inst = enc.Value;
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}
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class MxMove_RR<MxType TYPE, string DST_REG, string SRC_REG,
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MxMoveEncoding ENC,
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MxOpBundle DST = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_REG),
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MxOpBundle SRC = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#SRC_REG)>
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: MxMove<TYPE.Prefix,
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(outs DST.Op:$dst), (ins SRC.Op:$src),
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[(null_frag)], ENC>;
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let mayStore = 1 in {
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class MxMove_MR<MxOperand MEMOpd, ComplexPattern MEMPat, MxType REG,
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MxMoveEncoding ENC>
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: MxMove<REG.Prefix, (outs), (ins MEMOpd:$dst, REG.ROp:$src),
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[(store REG.VT:$src, MEMPat:$dst)], ENC>;
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class MxMove_MR<MxType TYPE, MxOpBundle DST, string SRC_REG, MxMoveEncoding ENC,
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MxOpBundle SRC = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#SRC_REG)>
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: MxMove<TYPE.Prefix, (outs), (ins DST.Op:$dst, SRC.Op:$src),
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[(store TYPE.VT:$src, DST.Pat:$dst)], ENC>;
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class MxMove_MI<MxOperand MEMOpd, ComplexPattern MEMPat, MxType TYPE,
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MxMoveEncoding ENC>
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: MxMove<TYPE.Prefix, (outs), (ins MEMOpd:$dst, TYPE.IOp:$src),
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[(store TYPE.IPat:$src, MEMPat:$dst)], ENC>;
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class MxMove_MI<MxType TYPE, MxOpBundle DST, MxMoveEncoding ENC,
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MxImmOpBundle SRC = !cast<MxImmOpBundle>("MxOp"#TYPE.Size#"AddrMode_i")>
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: MxMove<TYPE.Prefix, (outs), (ins DST.Op:$dst, SRC.Op:$src),
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[(store SRC.ImmPat:$src, DST.Pat:$dst)], ENC>;
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} // let mayStore = 1
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class MxMove_RI<MxType DST, MxMoveEncoding ENC>
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: MxMove<DST.Prefix, (outs DST.ROp:$dst), (ins DST.IOp:$src),
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[(set DST.VT:$dst, DST.IPat:$src)], ENC>;
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class MxMove_RI<MxType TYPE, string DST_REG, MxMoveEncoding ENC,
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MxImmOpBundle SRC = !cast<MxImmOpBundle>("MxOp"#TYPE.Size#"AddrMode_i"),
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MxOpBundle DST = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_REG)>
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: MxMove<TYPE.Prefix, (outs DST.Op:$dst), (ins SRC.Op:$src),
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[(set TYPE.VT:$dst, SRC.ImmPat:$src)], ENC>;
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let mayLoad = 1 in
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class MxMove_RM<MxType REG, MxOperand MEMOpd, ComplexPattern MEMPat,
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MxBead2Bits SIZE,
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MxEncEA SRCEA, MxEncExt SRCEXT,
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MxEncEA DSTEA, MxEncExt DSTEXT>
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: MxMove<REG.Prefix, (outs REG.ROp:$dst), (ins MEMOpd:$src),
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[(set REG.VT:$dst, (REG.Load MEMPat:$src))],
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MxMoveEncoding<SIZE, SRCEA, SRCEXT, DSTEA, DSTEXT>>;
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class MxMove_RM<MxType TYPE, string DST_REG, MxOpBundle SRC, MxEncMemOp SRC_ENC,
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MxMoveSize SIZE_ENC = !cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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MxOpBundle DST = !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_REG),
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MxEncMemOp DST_ENC = !cast<MxEncMemOp>("MxMoveDstOpEnc_"#DST_REG)>
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: MxMove<TYPE.Prefix, (outs DST.Op:$dst), (ins SRC.Op:$src),
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[(set TYPE.VT:$dst, (TYPE.Load SRC.Pat:$src))],
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MxMoveEncoding<SIZE_ENC, DST_ENC, SRC_ENC>>;
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multiclass MMxMove_RM<MxType REG, MxMoveSize SIZE, MxEncEA EA_0> {
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foreach REG = ["r", "a", "d"] in
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foreach AM = MxMoveSupportedAMs in {
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foreach TYPE = !if(!eq(REG, "d"), [MxType8, MxType16, MxType32], [MxType16, MxType32]) in
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def MOV # TYPE.Size # REG # AM # TYPE.Postfix
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: MxMove_RM<TYPE, REG, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM),
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#AM)>;
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} // foreach AM
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// REG <- (An)+
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def NAME#REG.OOp.Letter#REG.Postfix : MxMove_RM<REG, REG.OOp, REG.OPat,
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SIZE, MxEncEAo_1, MxExtEmpty, EA_0, MxExtEmpty>;
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let mayLoad = 1, mayStore = 1 in
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class MxMove_MM<MxType TYPE, MxOpBundle DST, MxOpBundle SRC,
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MxEncMemOp DST_ENC, MxEncMemOp SRC_ENC>
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: MxMove<TYPE.Prefix, (outs), (ins DST.Op:$dst, SRC.Op:$src),
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[(store (TYPE.Load SRC.Pat:$src), DST.Pat:$dst)],
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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DST_ENC, SRC_ENC>>;
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// REG <- -(An)
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def NAME#REG.EOp.Letter#REG.Postfix : MxMove_RM<REG, REG.EOp, REG.EPat,
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SIZE, MxEncEAe_1, MxExtEmpty, EA_0, MxExtEmpty>;
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foreach DST_AM = MxMoveSupportedAMs in
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foreach SRC_AM = MxMoveSupportedAMs in {
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foreach TYPE = [MxType8, MxType16, MxType32] in
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def MOV # TYPE.Size # DST_AM # SRC_AM # TYPE.Postfix
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: MxMove_MM<TYPE, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#DST_AM),
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!cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#SRC_AM),
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!cast<MxEncMemOp>("MxMoveDstOpEnc_"#DST_AM),
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#SRC_AM)>;
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} // foreach SRC_AM
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// REG <- (i,PC,Xn)
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def NAME#REG.KOp.Letter#REG.Postfix : MxMove_RM<REG, REG.KOp, REG.KPat,
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SIZE, MxEncEAk, MxExtBrief_1, EA_0, MxExtEmpty>;
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// REG <- (i,PC)
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def NAME#REG.QOp.Letter#REG.Postfix : MxMove_RM<REG, REG.QOp, REG.QPat,
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SIZE, MxEncEAq, MxExtI16_1, EA_0, MxExtEmpty>;
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// REG <- (i,An,Xn)
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def NAME#REG.FOp.Letter#REG.Postfix : MxMove_RM<REG, REG.FOp, REG.FPat,
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SIZE, MxEncEAf_1, MxExtBrief_1, EA_0, MxExtEmpty>;
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// REG <- (i,An)
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def NAME#REG.POp.Letter#REG.Postfix : MxMove_RM<REG, REG.POp, REG.PPat,
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SIZE, MxEncEAp_1, MxExtI16_1, EA_0, MxExtEmpty>;
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// REG <- (ABS)
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def NAME#REG.BOp.Letter#REG.Postfix : MxMove_RM<REG, REG.BOp, REG.BPat,
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SIZE, MxEncEAb, MxExtI32_1, EA_0, MxExtEmpty>;
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// REG <- (An)
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def NAME#REG.JOp.Letter#REG.Postfix : MxMove_RM<REG, REG.JOp, REG.JPat,
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SIZE, MxEncEAj_1, MxExtEmpty, EA_0, MxExtEmpty>;
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}
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let mayLoad = 1, mayStore = 1 in {
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class MxMove_MM<string SIZE, PatFrag LOAD,
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MxOperand DSTOpd, ComplexPattern DSTPat,
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MxOperand SRCOpd, ComplexPattern SRCPat,
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MxBead2Bits ESIZE,
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MxEncEA SRCEA, MxEncExt SRCEXT,
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MxEncEA DSTEA, MxEncExt DSTEXT>
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: MxMove<SIZE, (outs), (ins DSTOpd:$dst, SRCOpd:$src),
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[(store (LOAD SRCPat:$src), DSTPat:$dst)],
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MxMoveEncoding<ESIZE, SRCEA, SRCEXT, DSTEA, DSTEXT>>;
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} // let mayLoad = 1, mayStore = 1
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multiclass MMxMove_MM<MxType TYPE, MxOperand DSTOpd, ComplexPattern DSTPat,
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MxMoveSize SIZE, MxEncEA EA_0, MxEncExt EXT_0> {
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// MEM <- (An)+
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def NAME#TYPE.OOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.OOp, TYPE.OPat,
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SIZE, MxEncEAo_1, MxExtEmpty, EA_0, EXT_0>;
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// MEM <- -(An)
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def NAME#TYPE.EOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.EOp, TYPE.EPat,
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SIZE, MxEncEAe_1, MxExtEmpty, EA_0, EXT_0>;
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// MEM <- (i,An)
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def NAME#TYPE.POp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.POp, TYPE.PPat,
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SIZE, MxEncEAp_1, MxExtI16_1, EA_0, EXT_0>;
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// MEM <- (i,An,Xn)
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def NAME#TYPE.FOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.FOp, TYPE.FPat,
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SIZE, MxEncEAf_1, MxExtBrief_1, EA_0, EXT_0>;
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// MEM <- (i,PC,Xn)
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def NAME#TYPE.KOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.KOp, TYPE.KPat,
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SIZE, MxEncEAk, MxExtBrief_1, EA_0, EXT_0>;
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// MEM <- (i,PC)
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def NAME#TYPE.QOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.QOp, TYPE.QPat,
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SIZE, MxEncEAq, MxExtI16_1, EA_0, EXT_0>;
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// MEM <- (ABS)
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def NAME#TYPE.BOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.BOp, TYPE.BPat,
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SIZE, MxEncEAb, MxExtI32_1, EA_0, EXT_0>;
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// MEM <- (An)
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def NAME#TYPE.JOp.Letter#TYPE.Postfix
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: MxMove_MM<TYPE.Prefix, TYPE.Load, DSTOpd, DSTPat, TYPE.JOp, TYPE.JPat,
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SIZE, MxEncEAj_1, MxExtEmpty, EA_0, EXT_0>;
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}
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def MOV8dd
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: MxMove_RR<MxType8d, MxType8d,
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MxMoveEncoding<MxMoveSize8, MxEncEAd_1, MxExtEmpty, MxEncEAd_0, MxExtEmpty>>;
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// M <- R
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def MOV8fd : MxMove_MR<MxType8.FOp, MxType8.FPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAf_0, MxExtBrief_0>>;
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def MOV8pd : MxMove_MR<MxType8.POp, MxType8.PPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAp_0, MxExtI16_0>>;
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def MOV8ed : MxMove_MR<MxType8.EOp, MxType8.EPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAe_0, MxExtEmpty>>;
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def MOV8od : MxMove_MR<MxType8.OOp, MxType8.OPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAo_0, MxExtEmpty>>;
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def MOV8bd : MxMove_MR<MxType8.BOp, MxType8.BPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAb, MxExtI32_0>>;
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def MOV8jd : MxMove_MR<MxType8.JOp, MxType8.JPat, MxType8d,
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MxMoveEncoding<MxMoveSize8,
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/*src*/ MxEncEAd_1, MxExtEmpty,
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/*dst*/ MxEncEAj_0, MxExtEmpty>>;
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foreach DST_REG = ["r", "a"] in {
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foreach SRC_REG = ["r", "a"] in
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foreach TYPE = [MxType16, MxType32] in
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def MOV # TYPE.Size # DST_REG # SRC_REG # TYPE.Postfix
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: MxMove_RR<TYPE, DST_REG, SRC_REG,
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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!cast<MxEncMemOp>("MxMoveDstOpEnc_"#DST_REG),
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#SRC_REG)>>;
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} // foreach DST_REG
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foreach TYPE = [MxType8, MxType16, MxType32] in
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def MOV # TYPE.Size # dd # TYPE.Postfix
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: MxMove_RR<TYPE, "d", "d",
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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MxMoveDstOpEnc_d, MxMoveSrcOpEnc_d>>;
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// R <- I
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def MOV8di : MxMove_RI<MxType8d,
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MxMoveEncoding<MxMoveSize8, MxEncEAi, MxExtI8_1, MxEncEAd_0, MxExtEmpty>>;
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foreach REG = ["r", "a", "d"] in
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foreach AM = MxMoveSupportedAMs in {
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foreach TYPE = !if(!eq(REG, "d"), [MxType8, MxType16, MxType32], [MxType16, MxType32]) in
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def MOV # TYPE.Size # AM # REG # TYPE.Postfix
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: MxMove_MR<TYPE, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM), REG,
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
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!cast<MxEncMemOp>("MxMoveDstOpEnc_"#AM),
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!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#REG)>>;
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} // foreach AM
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foreach S = [16, 32] in {
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foreach D = [ "r", "a" ] in {
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foreach REG = ["r", "a", "d"] in {
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foreach TYPE = !if(!eq(REG, "d"), [MxType8, MxType16, MxType32], [MxType16, MxType32]) in
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def MOV # TYPE.Size # REG # i # TYPE.Postfix
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: MxMove_RI<TYPE, REG,
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MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
|
||||
!cast<MxEncMemOp>("MxMoveDstOpEnc_"#REG),
|
||||
MxEncAddrMode_i<"src", TYPE.Size>>>;
|
||||
} // foreach REG
|
||||
|
||||
foreach O = [ "r", "a" ] in {
|
||||
def MOV#S#D#O : MxMove_RR<
|
||||
!cast<MxType>("MxType"#S#D),
|
||||
!cast<MxType>("MxType"#S#O),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
|
||||
!cast<MxEncEA>("MxEncEA"#D#"_0_reflected"), MxExtEmpty>>;
|
||||
}
|
||||
|
||||
// M <- R
|
||||
def MOV#S#"f"#D : MxMove_MR<
|
||||
!cast<MxType>("MxType"#S).FOp,
|
||||
!cast<MxType>("MxType"#S).FPat,
|
||||
!cast<MxType>("MxType"#S#D),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
|
||||
MxEncEAf_0, MxExtBrief_0>>;
|
||||
|
||||
def MOV#S#"p"#D : MxMove_MR<
|
||||
!cast<MxType>("MxType"#S).POp,
|
||||
!cast<MxType>("MxType"#S).PPat,
|
||||
!cast<MxType>("MxType"#S#D),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
|
||||
MxEncEAp_0, MxExtI16_0>>;
|
||||
|
||||
def MOV#S#"e"#D : MxMove_MR<
|
||||
!cast<MxType>("MxType"#S).EOp,
|
||||
!cast<MxType>("MxType"#S).EPat,
|
||||
!cast<MxType>("MxType"#S#D),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
|
||||
MxEncEAe_0, MxExtEmpty>>;
|
||||
|
||||
def MOV#S#"o"#D : MxMove_MR<
|
||||
!cast<MxType>("MxType"#S).OOp,
|
||||
!cast<MxType>("MxType"#S).OPat,
|
||||
!cast<MxType>("MxType"#S#D),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
|
||||
MxEncEAo_0, MxExtEmpty>>;
|
||||
|
||||
def MOV#S#"b"#D : MxMove_MR<
|
||||
!cast<MxType>("MxType"#S).BOp,
|
||||
!cast<MxType>("MxType"#S).BPat,
|
||||
!cast<MxType>("MxType"#S#D),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
|
||||
MxEncEAb, MxExtI32_0>>;
|
||||
|
||||
def MOV#S#"j"#D : MxMove_MR<
|
||||
!cast<MxType>("MxType"#S).JOp,
|
||||
!cast<MxType>("MxType"#S).JPat,
|
||||
!cast<MxType>("MxType"#S#D),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
!cast<MxEncEA>("MxEncEA"#D#"_1"), MxExtEmpty,
|
||||
MxEncEAj_0, MxExtEmpty>>;
|
||||
|
||||
|
||||
// R <- I
|
||||
def MOV#S#D#"i" : MxMove_RI<
|
||||
!cast<MxType>("MxType"#S#D),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
|
||||
!cast<MxEncEA>("MxEncEA"#D#"_0_reflected"), MxExtEmpty>>;
|
||||
}
|
||||
}
|
||||
|
||||
// M <- I
|
||||
foreach S = [8, 16, 32] in {
|
||||
def MOV#S#"f"#"i" : MxMove_MI<
|
||||
!cast<MxType>("MxType"#S).FOp,
|
||||
!cast<MxType>("MxType"#S).FPat,
|
||||
!cast<MxType>("MxType"#S),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
|
||||
MxEncEAf_0, MxExtBrief_0>>;
|
||||
|
||||
def MOV#S#"p"#"i" : MxMove_MI<
|
||||
!cast<MxType>("MxType"#S).POp,
|
||||
!cast<MxType>("MxType"#S).PPat,
|
||||
!cast<MxType>("MxType"#S),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
|
||||
MxEncEAp_0, MxExtI16_0>>;
|
||||
|
||||
def MOV#S#"b"#"i" : MxMove_MI<
|
||||
!cast<MxType>("MxType"#S).BOp,
|
||||
!cast<MxType>("MxType"#S).BPat,
|
||||
!cast<MxType>("MxType"#S),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
|
||||
MxEncEAb, MxExtI32_0>>;
|
||||
|
||||
def MOV#S#"j"#"i" : MxMove_MI<
|
||||
!cast<MxType>("MxType"#S).JOp,
|
||||
!cast<MxType>("MxType"#S).JPat,
|
||||
!cast<MxType>("MxType"#S),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#S),
|
||||
MxEncEAi, !cast<MxEncExt>("MxExtI"#S#"_1"),
|
||||
MxEncEAj_0, MxExtEmpty>>;
|
||||
}
|
||||
foreach AM = MxMoveSupportedAMs in {
|
||||
foreach TYPE = [MxType8, MxType16, MxType32] in
|
||||
def MOV # TYPE.Size # AM # i # TYPE.Postfix
|
||||
: MxMove_MI<TYPE, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM),
|
||||
MxMoveEncoding<!cast<MxMoveSize>("MxMoveSize"#TYPE.Size),
|
||||
!cast<MxEncMemOp>("MxMoveDstOpEnc_"#AM),
|
||||
MxEncAddrMode_i<"src", TYPE.Size>>>;
|
||||
} // foreach AM
|
||||
|
||||
// Store ABS(basically pointer) as Immdiate to Mem
|
||||
def : Pat<(store MxType32.BPat :$src, MxType32.PPat :$dst),
|
||||
|
|
@ -340,65 +226,15 @@ def : Pat<(store MxType32.BPat :$src, MxType32.BPat :$dst),
|
|||
def : Pat<(store MxType32.BPat :$src, MxType32.JPat :$dst),
|
||||
(MOV32ji MxType32.JOp :$dst, MxType32.IOp :$src)>;
|
||||
|
||||
// R <- M
|
||||
defm MOV8d : MMxMove_RM<MxType8d, MxMoveSize8, MxEncEAd_0>;
|
||||
|
||||
defm MOV16r : MMxMove_RM<MxType16r, MxMoveSize16, MxEncEAr_0_reflected>;
|
||||
defm MOV16a : MMxMove_RM<MxType16a, MxMoveSize16, MxEncEAa_0>;
|
||||
|
||||
defm MOV32r : MMxMove_RM<MxType32r, MxMoveSize32, MxEncEAr_0_reflected>;
|
||||
defm MOV32a : MMxMove_RM<MxType32a, MxMoveSize32, MxEncEAa_0>;
|
||||
|
||||
let Pattern = [(null_frag)] in {
|
||||
defm MOV16r : MMxMove_RM<MxType16r_TC, MxMoveSize16, MxEncEAr_0_reflected>;
|
||||
defm MOV16a : MMxMove_RM<MxType16a_TC, MxMoveSize16, MxEncEAa_0>;
|
||||
|
||||
defm MOV32r : MMxMove_RM<MxType32r_TC, MxMoveSize32, MxEncEAr_0_reflected>;
|
||||
defm MOV32a : MMxMove_RM<MxType32a_TC, MxMoveSize32, MxEncEAa_0>;
|
||||
} // Pattern
|
||||
|
||||
// M <- M
|
||||
defm MOV8p : MMxMove_MM<MxType8, MxType8.POp, MxType8.PPat,
|
||||
MxMoveSize8, MxEncEAp_0, MxExtI16_0>;
|
||||
defm MOV16p : MMxMove_MM<MxType16, MxType16.POp, MxType16.PPat,
|
||||
MxMoveSize16, MxEncEAp_0, MxExtI16_0>;
|
||||
defm MOV32p : MMxMove_MM<MxType32, MxType32.POp, MxType32.PPat,
|
||||
MxMoveSize32, MxEncEAp_0, MxExtI16_0>;
|
||||
|
||||
defm MOV8f : MMxMove_MM<MxType8, MxType8.FOp, MxType8.FPat,
|
||||
MxMoveSize8, MxEncEAf_0, MxExtBrief_0>;
|
||||
defm MOV16f : MMxMove_MM<MxType16, MxType16.FOp, MxType16.FPat,
|
||||
MxMoveSize16, MxEncEAf_0, MxExtBrief_0>;
|
||||
defm MOV32f : MMxMove_MM<MxType32, MxType32.FOp, MxType32.FPat,
|
||||
MxMoveSize32, MxEncEAf_0, MxExtBrief_0>;
|
||||
|
||||
defm MOV8b : MMxMove_MM<MxType8, MxType8.BOp, MxType8.BPat,
|
||||
MxMoveSize8, MxEncEAb, MxExtI32_0>;
|
||||
defm MOV16b : MMxMove_MM<MxType16, MxType16.BOp, MxType16.BPat,
|
||||
MxMoveSize16, MxEncEAb, MxExtI32_0>;
|
||||
defm MOV32b : MMxMove_MM<MxType32, MxType32.BOp, MxType32.BPat,
|
||||
MxMoveSize32, MxEncEAb, MxExtI32_0>;
|
||||
|
||||
defm MOV8e : MMxMove_MM<MxType8, MxType8.EOp, MxType8.EPat,
|
||||
MxMoveSize8, MxEncEAe_0, MxExtEmpty>;
|
||||
defm MOV16e : MMxMove_MM<MxType16, MxType16.EOp, MxType16.EPat,
|
||||
MxMoveSize16, MxEncEAe_0, MxExtEmpty>;
|
||||
defm MOV32e : MMxMove_MM<MxType32, MxType32.EOp, MxType32.EPat,
|
||||
MxMoveSize32, MxEncEAe_0, MxExtEmpty>;
|
||||
|
||||
defm MOV8o : MMxMove_MM<MxType8, MxType8.OOp, MxType8.OPat,
|
||||
MxMoveSize8, MxEncEAo_0, MxExtEmpty>;
|
||||
defm MOV16o : MMxMove_MM<MxType16, MxType16.OOp, MxType16.OPat,
|
||||
MxMoveSize16, MxEncEAo_0, MxExtEmpty>;
|
||||
defm MOV32o : MMxMove_MM<MxType32, MxType32.OOp, MxType32.OPat,
|
||||
MxMoveSize32, MxEncEAo_0, MxExtEmpty>;
|
||||
|
||||
defm MOV8j : MMxMove_MM<MxType8, MxType8.JOp, MxType8.JPat,
|
||||
MxMoveSize8, MxEncEAj_0, MxExtEmpty>;
|
||||
defm MOV16j : MMxMove_MM<MxType16, MxType16.JOp, MxType16.JPat,
|
||||
MxMoveSize16, MxEncEAj_0, MxExtEmpty>;
|
||||
defm MOV32j : MMxMove_MM<MxType32, MxType32.JOp, MxType32.JPat,
|
||||
MxMoveSize32, MxEncEAj_0, MxExtEmpty>;
|
||||
foreach REG = ["r", "a"] in
|
||||
foreach AM = MxMoveSupportedAMs in {
|
||||
foreach TYPE = [MxType16, MxType32] in
|
||||
def MOV # TYPE.Size # REG # AM # _TC
|
||||
: MxMove_RM<TYPE, REG, !cast<MxOpBundle>("MxOp"#TYPE.Size#"AddrMode_"#AM),
|
||||
!cast<MxEncMemOp>("MxMoveSrcOpEnc_"#AM)>;
|
||||
} // foreach AM
|
||||
} // let Pattern
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// MOVEM
|
||||
|
|
|
|||
|
|
@ -263,6 +263,16 @@ class MxEncBriefExt<string reg_opnd, string disp_opnd,
|
|||
);
|
||||
}
|
||||
|
||||
class MxEncAddrMode_d<string reg_opnd> : MxEncMemOp {
|
||||
let EA = (descend /*MODE*/0b000,
|
||||
/*REGISTER*/(operand "$"#reg_opnd, 3));
|
||||
}
|
||||
|
||||
class MxEncAddrMode_a<string reg_opnd> : MxEncMemOp {
|
||||
let EA = (descend /*MODE*/0b001,
|
||||
/*REGISTER*/(operand "$"#reg_opnd, 3));
|
||||
}
|
||||
|
||||
class MxEncAddrMode_r<string reg_opnd> : MxEncMemOp {
|
||||
let EA = (descend /*MODE without the last bit*/0b00,
|
||||
/*REGISTER with D/A bit*/(operand "$"#reg_opnd, 4));
|
||||
|
|
@ -327,7 +337,11 @@ class MxEncAddrMode_i<string opnd_name, int size> : MxEncMemOp {
|
|||
// abs.L -> size_w_l = true
|
||||
class MxEncAddrMode_abs<string opnd_name, bit size_w_l = false> : MxEncMemOp {
|
||||
let EA = (descend /*MODE*/0b111,
|
||||
/*REGISTER*/0b00, size_w_l);
|
||||
// Wrap the REGISTER part in another dag to make sure
|
||||
// the dag assigned to EA only has two arguments. Such
|
||||
// that it's easier for MOV instructions to reverse
|
||||
// on its destination part.
|
||||
/*REGISTER*/(descend 0b00, size_w_l));
|
||||
|
||||
// Absolute address
|
||||
let Supplement = !if(size_w_l,
|
||||
|
|
|
|||
|
|
@ -639,6 +639,74 @@ class MxType<ValueType vt, string prefix, string postfix,
|
|||
PatFrag Load = load;
|
||||
}
|
||||
|
||||
// Provides an alternative way to access the MxOperand and
|
||||
// patterns w.r.t a specific addressing mode.
|
||||
class MxOpBundle<int size, MxOperand op, ComplexPattern pat> {
|
||||
int Size = size;
|
||||
MxOperand Op = op;
|
||||
ComplexPattern Pat = pat;
|
||||
}
|
||||
|
||||
class MxImmOpBundle<int size, MxOperand op, PatFrag pat>
|
||||
: MxOpBundle<size, op, ?> {
|
||||
PatFrag ImmPat = pat;
|
||||
}
|
||||
|
||||
// TODO: We can use MxOp<S>AddrMode_<AM> in more places to
|
||||
// replace MxType-based operand factoring.
|
||||
foreach size = [8, 16, 32] in {
|
||||
// Dn
|
||||
def MxOp#size#AddrMode_d
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxDRD"#size), ?>;
|
||||
|
||||
// (An)
|
||||
def MxOp#size#AddrMode_j
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxARI"#size), MxCP_ARI>;
|
||||
|
||||
// (An)+
|
||||
def MxOp#size#AddrMode_o
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxARIPI"#size), MxCP_ARIPI>;
|
||||
|
||||
// -(An)
|
||||
def MxOp#size#AddrMode_e
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxARIPD"#size), MxCP_ARIPD>;
|
||||
|
||||
// (i,An)
|
||||
def MxOp#size#AddrMode_p
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxARID"#size), MxCP_ARID>;
|
||||
|
||||
// (i,An,Xn)
|
||||
def MxOp#size#AddrMode_f
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxARII"#size), MxCP_ARII>;
|
||||
|
||||
// (ABS).L
|
||||
def MxOp#size#AddrMode_b
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxAL"#size), MxCP_AL>;
|
||||
|
||||
// (i,PC)
|
||||
def MxOp#size#AddrMode_q
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxPCD"#size), MxCP_PCD>;
|
||||
|
||||
// (i,PC,Xn)
|
||||
def MxOp#size#AddrMode_k
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxPCI"#size), MxCP_PCI>;
|
||||
|
||||
// #imm
|
||||
def MxOp#size#AddrMode_i
|
||||
: MxImmOpBundle<size, !cast<MxOperand>("Mxi"#size#"imm"),
|
||||
!cast<PatFrag>("MximmSExt"#size)>;
|
||||
} // foreach size = [8, 16, 32]
|
||||
|
||||
foreach size = [16, 32] in {
|
||||
// An
|
||||
def MxOp#size#AddrMode_a
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxARD"#size), ?>;
|
||||
|
||||
// Xn
|
||||
def MxOp#size#AddrMode_r
|
||||
: MxOpBundle<size, !cast<MxOperand>("MxXRD"#size), ?>;
|
||||
} // foreach size = [16, 32]
|
||||
|
||||
class MxType8Class<string rLet, MxOperand reg>
|
||||
: MxType<i8, "b", "", rLet, reg,
|
||||
MxARI8, MxCP_ARI,
|
||||
|
|
|
|||
|
|
@ -102,9 +102,8 @@ define void @test5() nounwind {
|
|||
; CHECK-LABEL: test5:
|
||||
; CHECK: ; %bb.0: ; %entry
|
||||
; CHECK-NEXT: lea (dst6,%pc), %a0
|
||||
; CHECK-NEXT: lea (ptr6,%pc), %a1
|
||||
; CHECK-NEXT: move.l %a0, (%a1)
|
||||
; CHECK-NEXT: move.l (src6,%pc), (%a0)
|
||||
; CHECK-NEXT: move.l %a0, (ptr6,%pc)
|
||||
; CHECK-NEXT: move.l (src6,%pc), (dst6,%pc)
|
||||
; CHECK-NEXT: rts
|
||||
entry:
|
||||
store i32* @dst6, i32** @ptr6
|
||||
|
|
|
|||
|
|
@ -11,9 +11,8 @@ define void @test0() nounwind {
|
|||
; CHECK-LABEL: test0:
|
||||
; CHECK: ; %bb.0: ; %entry
|
||||
; CHECK-NEXT: lea (dst,%pc), %a0
|
||||
; CHECK-NEXT: lea (ptr,%pc), %a1
|
||||
; CHECK-NEXT: move.l %a0, (%a1)
|
||||
; CHECK-NEXT: move.l (src,%pc), (%a0)
|
||||
; CHECK-NEXT: move.l %a0, (ptr,%pc)
|
||||
; CHECK-NEXT: move.l (src,%pc), (dst,%pc)
|
||||
; CHECK-NEXT: rts
|
||||
entry:
|
||||
store i32* @dst, i32** @ptr
|
||||
|
|
@ -30,9 +29,8 @@ define void @test1() nounwind {
|
|||
; CHECK-LABEL: test1:
|
||||
; CHECK: ; %bb.0: ; %entry
|
||||
; CHECK-NEXT: lea (dst2,%pc), %a0
|
||||
; CHECK-NEXT: lea (ptr2,%pc), %a1
|
||||
; CHECK-NEXT: move.l %a0, (%a1)
|
||||
; CHECK-NEXT: move.l (src2,%pc), (%a0)
|
||||
; CHECK-NEXT: move.l %a0, (ptr2,%pc)
|
||||
; CHECK-NEXT: move.l (src2,%pc), (dst2,%pc)
|
||||
; CHECK-NEXT: rts
|
||||
entry:
|
||||
store i32* @dst2, i32** @ptr2
|
||||
|
|
@ -65,8 +63,7 @@ define void @test3() nounwind {
|
|||
; CHECK-NEXT: suba.l #4, %sp
|
||||
; CHECK-NEXT: jsr afoo@PLT
|
||||
; CHECK-NEXT: move.l %d0, %a0
|
||||
; CHECK-NEXT: lea (pfoo,%pc), %a1
|
||||
; CHECK-NEXT: move.l %a0, (%a1)
|
||||
; CHECK-NEXT: move.l %a0, (pfoo,%pc)
|
||||
; CHECK-NEXT: jsr (%a0)
|
||||
; CHECK-NEXT: adda.l #4, %sp
|
||||
; CHECK-NEXT: rts
|
||||
|
|
@ -100,9 +97,8 @@ define void @test5() nounwind {
|
|||
; CHECK-LABEL: test5:
|
||||
; CHECK: ; %bb.0: ; %entry
|
||||
; CHECK-NEXT: lea (dst6,%pc), %a0
|
||||
; CHECK-NEXT: lea (ptr6,%pc), %a1
|
||||
; CHECK-NEXT: move.l %a0, (%a1)
|
||||
; CHECK-NEXT: move.l (src6,%pc), (%a0)
|
||||
; CHECK-NEXT: move.l %a0, (ptr6,%pc)
|
||||
; CHECK-NEXT: move.l (src6,%pc), (dst6,%pc)
|
||||
; CHECK-NEXT: rts
|
||||
entry:
|
||||
store i32* @dst6, i32** @ptr6
|
||||
|
|
|
|||
|
|
@ -1,4 +1,7 @@
|
|||
# RUN: llvm-mc -disassemble -triple m68k %s | FileCheck %s
|
||||
# Disable this particular test until migration to the new code emitter is
|
||||
# finished.
|
||||
# XFAIL: *
|
||||
|
||||
# CHECK: move.l %a1, %a0
|
||||
0x20 0x49
|
||||
|
|
|
|||
Loading…
Reference in New Issue