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[Alignment][NFC] Use more Align versions of various functions 

Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, arsenm, sdardis, jvesely, nhaehnle, hiraditya, jrtc27, atanasyan, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77291
This commit is contained in:
Guillaume Chatelet 2020-04-02 08:53:29 +00:00
parent 550ab58bc1
commit 189d2e215f
8 changed files with 13 additions and 12 deletions
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4
llvm/lib/CodeGen/RegAllocFast.cpp
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@ -255,8 +255,8 @@ int RegAllocFast::getStackSpaceFor(Register VirtReg) {
// Allocate a new stack object for this spill location...
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
unsigned Size = TRI->getSpillSize(RC);
unsigned Align = TRI->getSpillAlignment(RC);
int FrameIdx = MFI->CreateSpillStackObject(Size, Align);
Align Alignment = TRI->getSpillAlign(RC);
int FrameIdx = MFI->CreateSpillStackObject(Size, Alignment);
// Assign the slot.
StackSlotForVirtReg[VirtReg] = FrameIdx;

4
llvm/lib/CodeGen/TargetLoweringBase.cpp
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@ -1530,7 +1530,7 @@ void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType,
/// alignment, not its logarithm.
unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty,
const DataLayout &DL) const {
return DL.getABITypeAlignment(Ty);
return DL.getABITypeAlign(Ty).value();
}
bool TargetLoweringBase::allowsMemoryAccessForAlignment(
@ -1542,7 +1542,7 @@ bool TargetLoweringBase::allowsMemoryAccessForAlignment(
// For example, the ABI alignment may change based on software platform while
// this function should only be affected by hardware implementation.
Type *Ty = VT.getTypeForEVT(Context);
if (Alignment >= DL.getABITypeAlignment(Ty)) {
if (Alignment >= DL.getABITypeAlign(Ty).value()) {
// Assume that an access that meets the ABI-specified alignment is fast.
if (Fast != nullptr)
*Fast = true;

4
llvm/lib/CodeGen/VirtRegMap.cpp
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@ -92,8 +92,8 @@ void VirtRegMap::assignVirt2Phys(Register virtReg, MCPhysReg physReg) {
unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
unsigned Size = TRI->getSpillSize(*RC);
unsigned Align = TRI->getSpillAlignment(*RC);
int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Align);
Align Alignment = TRI->getSpillAlign(*RC);
int SS = MF->getFrameInfo().CreateSpillStackObject(Size, Alignment);
++NumSpillSlots;
return SS;
}

2
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
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@ -323,7 +323,7 @@ bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
Optional<int> CSRSpillFI;
if ((FrameInfo.hasCalls() || !isEntryFunction()) && CSRegs &&
isCalleeSavedReg(CSRegs, LaneVGPR)) {
CSRSpillFI = FrameInfo.CreateSpillStackObject(4, 4);
CSRSpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
}
SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, CSRSpillFI));

4
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -17237,7 +17237,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
Info.memVT = MVT::getVT(PtrTy->getElementType());
Info.ptrVal = I.getArgOperand(0);
Info.offset = 0;
Info.align = MaybeAlign(DL.getABITypeAlignment(PtrTy->getElementType()));
Info.align = DL.getABITypeAlign(PtrTy->getElementType());
Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
return true;
}
@ -17249,7 +17249,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
Info.memVT = MVT::getVT(PtrTy->getElementType());
Info.ptrVal = I.getArgOperand(1);
Info.offset = 0;
Info.align = MaybeAlign(DL.getABITypeAlignment(PtrTy->getElementType()));
Info.align = DL.getABITypeAlign(PtrTy->getElementType());
Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
return true;
}

3
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
View File

@ -2163,7 +2163,8 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
Num = 2; // Vector predicate spills also need a vector register.
break;
}
unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC);
unsigned S = HRI.getSpillSize(*RC);
Align A = HRI.getSpillAlign(*RC);
for (unsigned i = 0; i < Num; i++) {
int NewFI = MFI.CreateSpillStackObject(S, A);
RS->addScavengingFrameIndex(NewFI);

2
llvm/lib/Target/Mips/MipsISelLowering.h
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@ -306,7 +306,7 @@ class TargetRegisterClass;
/// Return the correct alignment for the current calling convention.
Align getABIAlignmentForCallingConv(Type *ArgTy,
DataLayout DL) const override {
const Align ABIAlign(DL.getABITypeAlignment(ArgTy));
const Align ABIAlign = DL.getABITypeAlign(ArgTy);
if (ArgTy->isVectorTy())
return std::min(ABIAlign, Align(8));
return ABIAlign;

2
llvm/lib/Target/X86/X86FrameLowering.cpp
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@ -2177,7 +2177,7 @@ bool X86FrameLowering::assignCalleeSavedSpillSlots(
if (this->TRI->hasBasePointer(MF)) {
// Allocate a spill slot for EBP if we have a base pointer and EH funclets.
if (MF.hasEHFunclets()) {
int FI = MFI.CreateSpillStackObject(SlotSize, SlotSize);
int FI = MFI.CreateSpillStackObject(SlotSize, Align(SlotSize));
X86FI->setHasSEHFramePtrSave(true);
X86FI->setSEHFramePtrSaveIndex(FI);
}