forked from OSchip/llvm-project
ScheduleDAGInstrs: Skip debug instructions at end of scheduling region
If the end instruction of the scheduling region was a DBG_VALUE, the uses of the debug instruction were tracked as if they were real uses. This would then hit the deadDefHasNoUse assertion in addVRegDefDeps if the only use was the debug instruction.
This commit is contained in:
Matt Arsenault
parent
e3c6b0f151
commit
188df17420
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@ -199,7 +199,10 @@ void ScheduleDAGInstrs::exitRegion() {
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}
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void ScheduleDAGInstrs::addSchedBarrierDeps() {
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MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
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MachineInstr *ExitMI =
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RegionEnd != BB->end()
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? &*skipDebugInstructionsBackward(RegionEnd, RegionBegin)
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: nullptr;
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ExitSU.setInstr(ExitMI);
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// Add dependencies on the defs and uses of the instruction.
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if (ExitMI) {
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@ -511,6 +514,8 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
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/// TODO: Handle ExitSU "uses" properly.
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void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
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const MachineInstr *MI = SU->getInstr();
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assert(!MI->isDebugInstr());
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const MachineOperand &MO = MI->getOperand(OperIdx);
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Register Reg = MO.getReg();
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@ -0,0 +1,132 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s
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# The DBG_VALUE in bb.5 ends a scheduling region, and its uses should
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# not be tracked like a normal instruction.
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--- |
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define void @dbg_value_ends_sched_region() {
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unreachable
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}
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!3, !4}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 12.0.0 (/src/external/llvm-project/clang ff12a3768d17240b01cbe9957e3c9e8f8ffe9854)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, splitDebugInlining: false, nameTableKind: None)
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!1 = !DIFile(filename: "/tmp/comgr-054202/input/CompileSource", directory: "/home/matt/bugs/SWDEV-253507")
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!2 = !{}
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!3 = !{i32 2, !"Debug Info Version", i32 3}
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!4 = !{i32 7, !"PIC Level", i32 1}
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!5 = !{!6, !9, i64 68}
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!6 = !{!"ShaderData", !7, i64 0, !7, i64 16, !7, i64 32, !7, i64 48, !9, i64 64, !9, i64 68, !9, i64 72, !9, i64 76, !9, i64 80, !10, i64 84, !10, i64 88, !9, i64 92, !9, i64 96, !10, i64 100, !10, i64 104, !11, i64 112, !11, i64 144, !12, i64 176, !12, i64 184, !7, i64 192, !7, i64 208, !7, i64 224, !11, i64 240, !9, i64 272, !9, i64 276, !9, i64 280, !10, i64 284, !7, i64 288, !7, i64 304, !7, i64 320, !7, i64 336}
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!7 = !{!"omnipotent char", !8, i64 0}
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!8 = !{!"Simple C/C++ TBAA"}
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!9 = !{!"int", !7, i64 0}
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!10 = !{!"float", !7, i64 0}
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!11 = !{!"differential3", !7, i64 0, !7, i64 16}
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!12 = !{!"differential", !10, i64 0, !10, i64 4}
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!13 = !{!6, !9, i64 280}
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!16 = !DILocalVariable(name: "data", scope: !17, file: !18, line: 24)
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!17 = distinct !DISubprogram(name: "svm_node_geometry", scope: !18, file: !18, line: 21, type: !19, scopeLine: 23, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
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!18 = !DIFile(filename: "source/kernel/svm/svm_geometry.h", directory: "/home/matt/bugs/SWDEV-253507")
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!19 = !DISubroutineType(types: !20)
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!20 = !{null}
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!21 = !DILocation(line: 0, scope: !17)
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...
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---
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name: dbg_value_ends_sched_region
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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; CHECK-LABEL: name: dbg_value_ends_sched_region
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
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; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF6:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; CHECK: [[DEF8:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
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; CHECK: undef %11.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: dead %12:vreg_64 = COPY [[DEF]]
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; CHECK: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[DEF3]]
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; CHECK: dead %14:vgpr_32 = COPY [[DEF2]]
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; CHECK: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[DEF5]].sub1
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; CHECK: dead %16:vgpr_32 = COPY %11.sub0
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; CHECK: undef %17.sub0:vreg_64, %18:sreg_64_xexec = V_ADD_CO_U32_e64 [[DEF4]].sub0, [[DEF6]].sub0, 0, implicit $exec
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; CHECK: dead undef %17.sub1:vreg_64, dead %19:sreg_64_xexec = V_ADDC_U32_e64 [[DEF4]].sub1, [[DEF6]].sub1, %18, 0, implicit $exec
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; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF1]], 0, 0, 0, 0, implicit $exec :: (load 8, addrspace 1)
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; CHECK: dead %20:sreg_64 = V_CMP_GT_I32_e64 4, [[DEF7]], implicit $exec
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; CHECK: GLOBAL_STORE_DWORDX2 [[COPY]], [[DEF8]], 288, 0, 0, 0, implicit $exec :: (store 8, addrspace 1)
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
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; CHECK: bb.3:
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; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000)
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; CHECK: undef [[DEF5]].sub1:vreg_64 = COPY [[COPY3]]
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; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
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; CHECK: bb.4:
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; CHECK: successors: %bb.5(0x80000000)
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; CHECK: dead %21:sreg_64 = COPY $exec
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; CHECK: dead %22:vreg_128 = GLOBAL_LOAD_DWORDX4 [[COPY1]], 0, 0, 0, 0, implicit $exec :: (load 16, addrspace 1)
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; CHECK: DBG_VALUE %22,
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; CHECK: bb.5:
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; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; CHECK: S_CBRANCH_EXECZ %bb.3, implicit $exec
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; CHECK: S_BRANCH %bb.1
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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%0:vreg_64 = COPY $vgpr0_vgpr1
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%1:vreg_64 = COPY $vgpr2_vgpr3
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%2:vreg_64 = IMPLICIT_DEF
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%3:vreg_64 = IMPLICIT_DEF
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%4:vgpr_32 = IMPLICIT_DEF
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%5:vgpr_32 = IMPLICIT_DEF
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%6:vreg_64 = IMPLICIT_DEF
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%7:vreg_64 = IMPLICIT_DEF
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%8:vreg_64 = IMPLICIT_DEF
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%9:vgpr_32 = IMPLICIT_DEF
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%10:vreg_64 = IMPLICIT_DEF
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undef %11.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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bb.1:
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%12:vreg_64 = COPY %2
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%13:vgpr_32 = COPY %5
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dead %14:vgpr_32 = COPY %4
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%15:vgpr_32 = COPY %7.sub1
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dead %16:vgpr_32 = COPY %11.sub0
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undef %17.sub0:vreg_64, %18:sreg_64_xexec = V_ADD_CO_U32_e64 %6.sub0, %8.sub0, 0, implicit $exec
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dead %17.sub1:vreg_64, dead %19:sreg_64_xexec = V_ADDC_U32_e64 %6.sub1, %8.sub1, %18, 0, implicit $exec
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%6:vreg_64 = GLOBAL_LOAD_DWORDX2 %3, 0, 0, 0, 0, implicit $exec :: (load 8, addrspace 1)
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dead %20:sreg_64 = V_CMP_GT_I32_e64 4, %9, implicit $exec
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GLOBAL_STORE_DWORDX2 %0, %10, 288, 0, 0, 0, implicit $exec :: (store 8, addrspace 1)
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bb.2:
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%5:vgpr_32 = COPY %13
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bb.3:
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undef %7.sub1:vreg_64 = COPY %15
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S_CBRANCH_EXECZ %bb.2, implicit $exec
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bb.4:
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dead %21:sreg_64 = COPY $exec
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%22:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 0, 0, 0, 0, implicit $exec :: (load 16, addrspace 1)
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DBG_VALUE %22, $noreg, !16, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !21
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bb.5:
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S_CBRANCH_EXECZ %bb.3, implicit $exec
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S_BRANCH %bb.1
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...
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