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[InstCombine] Teach getDemandedBitsLHSMask to handle constant splat vectors 

This replaces a ConstantInt dyn_cast with m_APInt

Differential Revision: https://reviews.llvm.org/D38100

llvm-svn: 313840
This commit is contained in:
Craig Topper 2017-09-20 23:48:58 +00:00
parent eb0f71f232
commit 18887bf179
2 changed files with 10 additions and 16 deletions
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18
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
View File

@ -3926,26 +3926,22 @@ static APInt getDemandedBitsLHSMask(ICmpInst &I, unsigned BitWidth,
if (isSignCheck)
return APInt::getSignMask(BitWidth);
ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(1));
if (!CI) return APInt::getAllOnesValue(BitWidth);
const APInt &RHS = CI->getValue();
const APInt *RHS;
if (!match(I.getOperand(1), m_APInt(RHS)))
return APInt::getAllOnesValue(BitWidth);
switch (I.getPredicate()) {
// For a UGT comparison, we don't care about any bits that
// correspond to the trailing ones of the comparand. The value of these
// bits doesn't impact the outcome of the comparison, because any value
// greater than the RHS must differ in a bit higher than these due to carry.
case ICmpInst::ICMP_UGT: {
unsigned trailingOnes = RHS.countTrailingOnes();
return APInt::getBitsSetFrom(BitWidth, trailingOnes);
}
case ICmpInst::ICMP_UGT:
return APInt::getBitsSetFrom(BitWidth, RHS->countTrailingOnes());
// Similarly, for a ULT comparison, we don't care about the trailing zeros.
// Any value less than the RHS must differ in a higher bit because of carries.
case ICmpInst::ICMP_ULT: {
unsigned trailingZeros = RHS.countTrailingZeros();
return APInt::getBitsSetFrom(BitWidth, trailingZeros);
}
case ICmpInst::ICMP_ULT:
return APInt::getBitsSetFrom(BitWidth, RHS->countTrailingZeros());
default:
return APInt::getAllOnesValue(BitWidth);

8
llvm/test/Transforms/InstCombine/icmp.ll
View File

@ -1163,11 +1163,10 @@ define <2 x i1> @test67vec(<2 x i32> %x) {
ret <2 x i1> %cmp
}
; FIXME: Vector constant for the 'and' should use less bits.
define <2 x i1> @test67vec2(<2 x i32> %x) {
; CHECK-LABEL: @test67vec2(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %x, <i32 127, i32 127>
; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[AND]], <i32 31, i32 31>
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], <i32 96, i32 96>
; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i32> [[AND]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%and = and <2 x i32> %x, <i32 127, i32 127>
@ -1997,10 +1996,9 @@ define i1 @shrink_constant(i32 %X) {
ret i1 %cmp
}
; FIXME: This doesn't change because of a limitation in 'DemandedBitsLHSMask'.
define <2 x i1> @shrink_constant_vec(<2 x i32> %X) {
; CHECK-LABEL: @shrink_constant_vec(
; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> %X, <i32 -9, i32 -9>
; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[X:%.*]], <i32 -12, i32 -12>
; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[XOR]], <i32 4, i32 4>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;