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Add emulation methods for "SBC (immediate)" and "SBC (register)" operations. 

llvm-svn: 126283
This commit is contained in:
Johnny Chen 2011-02-23 01:01:21 +00:00
parent b51f65c297
commit 187b0e37c1
2 changed files with 170 additions and 4 deletions
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166
lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
View File

@ -6165,6 +6165,163 @@ EmulateInstructionARM::EmulateRSCReg (ARMEncoding encoding)
return true;
}
// Subtract with Carry (immediate) subtracts an immediate value and the value of
// NOT (Carry flag) from a register value, and writes the result to the destination register.
// It can optionally update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateSBCImm (ARMEncoding encoding)
{
#if 0
// ARM pseudo code...
if ConditionPassed() then
EncodingSpecificOperations();
(result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), APSR.C);
if d == 15 then // Can only occur for ARM encoding
ALUWritePC(result); // setflags is always FALSE here
else
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
APSR.V = overflow;
#endif
bool success = false;
const uint32_t opcode = OpcodeAsUnsigned (&success);
if (!success)
return false;
uint32_t Rd; // the destination register
uint32_t Rn; // the first operand
bool setflags;
uint32_t imm32; // the immediate value to be added to the value obtained from Rn
switch (encoding) {
case eEncodingT1:
Rd = Bits32(opcode, 11, 8);
Rn = Bits32(opcode, 19, 16);
setflags = BitIsSet(opcode, 20);
imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
if (BadReg(Rd) || BadReg(Rn))
return false;
break;
case eEncodingA1:
Rd = Bits32(opcode, 15, 12);
Rn = Bits32(opcode, 19, 16);
setflags = BitIsSet(opcode, 20);
imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
// if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
// TODO: Emulate SUBS PC, LR and related instructions.
if (Rd == 15 && setflags)
return false;
break;
default:
return false;
}
// Read the register value from the operand register Rn.
uint32_t reg_val = ReadCoreReg(Rn, &success);
if (!success)
return false;
AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, APSR_C);
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextImmediate;
context.SetNoArgs ();
if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
return false;
return true;
}
// Subtract with Carry (register) subtracts an optionally-shifted register value and the value of
// NOT (Carry flag) from a register value, and writes the result to the destination register.
// It can optionally update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateSBCReg (ARMEncoding encoding)
{
#if 0
// ARM pseudo code...
if ConditionPassed() then
EncodingSpecificOperations();
shifted = Shift(R[m], shift_t, shift_n, APSR.C);
(result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), APSR.C);
if d == 15 then // Can only occur for ARM encoding
ALUWritePC(result); // setflags is always FALSE here
else
R[d] = result;
if setflags then
APSR.N = result<31>;
APSR.Z = IsZeroBit(result);
APSR.C = carry;
APSR.V = overflow;
#endif
bool success = false;
const uint32_t opcode = OpcodeAsUnsigned (&success);
if (!success)
return false;
uint32_t Rd; // the destination register
uint32_t Rn; // the first operand
uint32_t Rm; // the second operand
bool setflags;
ARM_ShifterType shift_t;
uint32_t shift_n; // the shift applied to the value read from Rm
switch (encoding) {
case eEncodingT1:
Rd = Rn = Bits32(opcode, 2, 0);
Rm = Bits32(opcode, 5, 3);
setflags = !InITBlock();
shift_t = SRType_LSL;
shift_n = 0;
break;
case eEncodingT2:
Rd = Bits32(opcode, 11, 8);
Rn = Bits32(opcode, 19, 16);
Rm = Bits32(opcode, 3, 0);
setflags = BitIsSet(opcode, 20);
shift_n = DecodeImmShiftThumb(opcode, shift_t);
if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
return false;
break;
case eEncodingA1:
Rd = Bits32(opcode, 15, 12);
Rn = Bits32(opcode, 19, 16);
Rm = Bits32(opcode, 3, 0);
setflags = BitIsSet(opcode, 20);
shift_n = DecodeImmShiftARM(opcode, shift_t);
// if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
// TODO: Emulate SUBS PC, LR and related instructions.
if (Rd == 15 && setflags)
return false;
break;
default:
return false;
}
// Read the register value from register Rn.
uint32_t val1 = ReadCoreReg(Rn, &success);
if (!success)
return false;
// Read the register value from register Rm.
uint32_t val2 = ReadCoreReg(Rm, &success);
if (!success)
return false;
uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C);
AddWithCarryResult res = AddWithCarry(val1, ~shifted, APSR_C);
EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextImmediate;
context.SetNoArgs();
if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
return false;
return true;
}
// Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an
// immediate value. It updates the condition flags based on the result, and discards the result.
bool
@ -6517,6 +6674,10 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
{ 0x0fe00000, 0x02e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSCImm, "rsc{s}<c> <Rd>, <Rn>, #<const>"},
// rsc (register)
{ 0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateRSCReg, "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
// sbc (immediate)
{ 0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
// sbc (register)
{ 0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
// teq (immediate)
{ 0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #const"},
// teq (register)
@ -6703,6 +6864,11 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
{ 0xfbe08000, 0xf1c00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c>.w <Rd>, <Rn>, #<const>"},
// rsb (register)
{ 0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateRSBReg, "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
// sbc (immediate)
{ 0xfbe08000, 0xf1600000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
// sbc (register)
{ 0xffffffc0, 0x00004180, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc<c> <Rdn>, <Rm>"},
{ 0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSBCReg, "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
// teq (immediate)
{ 0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #<const>"},
// teq (register)

8
lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
View File

@ -669,13 +669,13 @@ protected:
bool
EmulateRSCReg (ARMEncoding encoding);
// A8.6.150 SBC (immediate) - Encoding A1
// A8.6.150 SBC (immediate)
bool
EmulateSBCImmediate (ARMEncoding encoding);
EmulateSBCImm (ARMEncoding encoding);
// A8.6.151 SBC (register) - Encoding T1, A1
// A8.6.151 SBC (register)
bool
EmulateSBCRegister (ARMEncoding encoding);
EmulateSBCReg (ARMEncoding encoding);
// A8.6.210 SUB (immediate, Thumb) - Encoding T1, T2
bool