forked from OSchip/llvm-project
Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be enough for caller to allocate one.
llvm-svn: 124949
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b21c3db920
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1850c80afb
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@ -397,11 +397,6 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
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if (HasFP) MinSize += SlotSize;
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StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
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MFI->setStackSize(StackSize);
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} else if (IsWin64) {
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// We need to always allocate 32 bytes as register spill area.
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// FIXME: We might reuse these 32 bytes for leaf functions.
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StackSize += 32;
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MFI->setStackSize(StackSize);
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}
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// Insert stack pointer adjustment for later moving of return addr. Only
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@ -28,8 +28,7 @@ public:
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explicit X86FrameLowering(const X86TargetMachine &tm, const X86Subtarget &sti)
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: TargetFrameLowering(StackGrowsDown,
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sti.getStackAlignment(),
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(sti.isTargetWin64() ? -40 :
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(sti.is64Bit() ? -8 : -4))),
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(sti.is64Bit() ? -8 : -4)),
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TM(tm), STI(sti) {
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}
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@ -1544,6 +1544,12 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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// Allocate shadow area for Win64
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if (IsWin64) {
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CCInfo.AllocateStack(32, 8);
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}
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CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
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unsigned LastVal = ~0U;
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@ -1778,8 +1784,7 @@ X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
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DebugLoc dl, SelectionDAG &DAG,
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const CCValAssign &VA,
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ISD::ArgFlagsTy Flags) const {
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const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
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unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
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unsigned LocMemOffset = VA.getLocMemOffset();
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SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
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PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
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if (Flags.isByVal())
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@ -1864,6 +1869,12 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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// Allocate shadow area for Win64
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if (IsWin64) {
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CCInfo.AllocateStack(32, 8);
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}
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CCInfo.AnalyzeCallOperands(Outs, CC_X86);
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// Get a count of how many bytes are to be pushed on the stack.
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@ -2447,6 +2458,12 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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// Allocate shadow area for Win64
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if (Subtarget->isTargetWin64()) {
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CCInfo.AllocateStack(32, 8);
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}
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CCInfo.AnalyzeCallOperands(Outs, CC_X86);
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if (CCInfo.getNextStackOffset()) {
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MachineFunction &MF = DAG.getMachineFunction();
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@ -1,9 +1,8 @@
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; RUN: llc < %s | grep "subq.*\\\$40, \\\%rsp"
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target triple = "x86_64-pc-mingw64"
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; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s
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; CHECK-NOT: -{{[1-9][0-9]*}}(%rsp)
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define x86_fp80 @a(i64 %x) nounwind readnone {
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entry:
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%conv = sitofp i64 %x to x86_fp80 ; <x86_fp80> [#uses=1]
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ret x86_fp80 %conv
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%conv = sitofp i64 %x to x86_fp80 ; <x86_fp80> [#uses=1]
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ret x86_fp80 %conv
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}
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@ -1,12 +1,10 @@
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; RUN: llc < %s -o %t1
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; RUN: grep "subq.*\\\$72, \\\%rsp" %t1
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; RUN: grep "movaps \\\%xmm8, 32\\\(\\\%rsp\\\)" %t1
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; RUN: grep "movaps \\\%xmm7, 48\\\(\\\%rsp\\\)" %t1
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target triple = "x86_64-pc-mingw64"
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; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s
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; CHECK: subq $40, %rsp
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; CHECK: movaps %xmm8, (%rsp)
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; CHECK: movaps %xmm7, 16(%rsp)
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define i32 @a() nounwind {
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entry:
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tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind
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ret i32 undef
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tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind
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ret i32 undef
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}
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@ -4,8 +4,8 @@
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; on the stack.
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define i32 @f6(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize {
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entry:
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; CHECK: movl 80(%rsp), %eax
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; CHECK: addl 72(%rsp), %eax
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; CHECK: movl 48(%rsp), %eax
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; CHECK: addl 40(%rsp), %eax
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%add = add nsw i32 %p6, %p5
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ret i32 %add
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}
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@ -5,11 +5,11 @@
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; calculated.
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define void @average_va(i32 %count, ...) nounwind {
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entry:
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; CHECK: subq $40, %rsp
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; CHECK: movq %r9, 72(%rsp)
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; CHECK: movq %r8, 64(%rsp)
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; CHECK: movq %rdx, 56(%rsp)
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; CHECK: leaq 56(%rsp), %rax
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; CHECK: pushq
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; CHECK: movq %r9, 40(%rsp)
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; CHECK: movq %r8, 32(%rsp)
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; CHECK: movq %rdx, 24(%rsp)
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; CHECK: leaq 24(%rsp), %rax
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%ap = alloca i8*, align 8 ; <i8**> [#uses=1]
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%ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
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