forked from OSchip/llvm-project
[PowerPC] add tests for vector select-of-constants; NFC
We've discussed canonicalizing to this form in IR, so the backend should be prepared to lower these in ways better than what we see here. llvm-svn: 311099
This commit is contained in:
Sanjay Patel
parent
6a57daad81
commit
18424e1581
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
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; First, check the generic pattern for any 2 vector constants. Then, check special cases where
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; the constants are all off-by-one. Finally, check the extra special cases where the constants
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; include 0 or -1.
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; Each minimal select test is repeated with a more typical pattern that includes a compare to
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; generate the condition value.
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define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_C1_or_C2_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LCPI0_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l
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; CHECK-NEXT: addi 4, 4, .LCPI0_1@toc@l
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; CHECK-NEXT: lvx 18, 0, 3
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; CHECK-NEXT: lvx 19, 0, 4
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxsel 34, 51, 50, 34
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; CHECK-NEXT: blr
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%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_C1_or_C2_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LCPI1_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l
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; CHECK-NEXT: addi 4, 4, .LCPI1_1@toc@l
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; CHECK-NEXT: lvx 19, 0, 3
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; CHECK-NEXT: lvx 4, 0, 4
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; CHECK-NEXT: xxsel 34, 36, 51, 34
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; CHECK-NEXT: blr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_Cplus1_or_C_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LCPI2_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI2_0@toc@l
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; CHECK-NEXT: addi 4, 4, .LCPI2_1@toc@l
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; CHECK-NEXT: lvx 18, 0, 3
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; CHECK-NEXT: lvx 19, 0, 4
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxsel 34, 51, 50, 34
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; CHECK-NEXT: blr
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: addis 3, 2, .LCPI3_0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LCPI3_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI3_0@toc@l
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; CHECK-NEXT: addi 4, 4, .LCPI3_1@toc@l
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; CHECK-NEXT: lvx 19, 0, 3
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; CHECK-NEXT: lvx 4, 0, 4
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; CHECK-NEXT: xxsel 34, 36, 51, 34
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; CHECK-NEXT: blr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_Cminus1_or_C_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: addis 3, 2, .LCPI4_0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LCPI4_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI4_0@toc@l
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; CHECK-NEXT: addi 4, 4, .LCPI4_1@toc@l
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; CHECK-NEXT: lvx 18, 0, 3
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; CHECK-NEXT: lvx 19, 0, 4
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxsel 34, 51, 50, 34
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; CHECK-NEXT: blr
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: addis 3, 2, .LCPI5_0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LCPI5_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI5_0@toc@l
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; CHECK-NEXT: addi 4, 4, .LCPI5_1@toc@l
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; CHECK-NEXT: lvx 19, 0, 3
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; CHECK-NEXT: lvx 4, 0, 4
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; CHECK-NEXT: xxsel 34, 36, 51, 34
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; CHECK-NEXT: blr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_minus1_or_0_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: vspltisb 19, -1
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; CHECK-NEXT: xxlxor 0, 0, 0
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxsel 34, 0, 51, 34
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; CHECK-NEXT: blr
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%add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_minus1_or_0_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: vspltisb 19, -1
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; CHECK-NEXT: xxlxor 0, 0, 0
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; CHECK-NEXT: xxsel 34, 0, 51, 34
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; CHECK-NEXT: blr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_0_or_minus1_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: vspltisb 19, -1
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; CHECK-NEXT: xxlxor 0, 0, 0
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxsel 34, 51, 0, 34
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; CHECK-NEXT: blr
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_0_or_minus1_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: vspltisb 19, -1
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; CHECK-NEXT: xxlxor 0, 0, 0
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; CHECK-NEXT: xxsel 34, 51, 0, 34
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; CHECK-NEXT: blr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_1_or_0_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: vspltisw 19, 1
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; CHECK-NEXT: xxlxor 0, 0, 0
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxsel 34, 0, 51, 34
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; CHECK-NEXT: blr
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%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_1_or_0_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: vspltisw 19, 1
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; CHECK-NEXT: xxlxor 0, 0, 0
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; CHECK-NEXT: xxsel 34, 0, 51, 34
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; CHECK-NEXT: blr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %add
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}
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define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {
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; CHECK-LABEL: sel_0_or_1_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 15
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; CHECK-NEXT: vspltisw 19, 1
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; CHECK-NEXT: xxlxor 0, 0, 0
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vslw 2, 2, 3
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; CHECK-NEXT: vsraw 2, 2, 3
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; CHECK-NEXT: xxsel 34, 51, 0, 34
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; CHECK-NEXT: blr
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: cmp_sel_0_or_1_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpequw 2, 2, 3
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; CHECK-NEXT: vspltisw 19, 1
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; CHECK-NEXT: xxlxor 0, 0, 0
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; CHECK-NEXT: xxsel 34, 51, 0, 34
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; CHECK-NEXT: blr
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%cond = icmp eq <4 x i32> %x, %y
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%add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %add
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}
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