forked from OSchip/llvm-project
[HLSL] Add abs library function
This change exposes the abs library function for HLSL scalar types. Abs is supported for all scalar, vector and matrix types. This patch only adds a subset of scalar type support. Fixes #57100 (https://llvm.org/pr57100) The full documentation of the HLSL abs function is available here: https://docs.microsoft.com/en-us/windows/win32/direct3dhlsl/dx-graphics-hlsl-abs Reviewed By: bogner Differential Revision: https://reviews.llvm.org/D131718
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@ -495,6 +495,7 @@ defvar render_script = LangOpts<"RenderScript">;
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defvar hip = LangOpts<"HIP">;
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defvar gnu_mode = LangOpts<"GNUMode">;
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defvar asm_preprocessor = LangOpts<"AsmPreprocessor">;
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defvar hlsl = LangOpts<"HLSL">;
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defvar std = !strconcat("LangStandard::getLangStandardForKind(", lang_std.KeyPath, ")");
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@ -6134,7 +6135,7 @@ def fnative_half_type: Flag<["-"], "fnative-half-type">,
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def fnative_half_arguments_and_returns : Flag<["-"], "fnative-half-arguments-and-returns">,
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HelpText<"Use the native __fp16 type for arguments and returns (and skip ABI-specific lowering)">,
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MarshallingInfoFlag<LangOpts<"NativeHalfArgsAndReturns">>,
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ImpliedByAnyOf<[open_cl.KeyPath, render_script.KeyPath]>;
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ImpliedByAnyOf<[open_cl.KeyPath, render_script.KeyPath, hlsl.KeyPath]>;
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def fallow_half_arguments_and_returns : Flag<["-"], "fallow-half-arguments-and-returns">,
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HelpText<"Allow function arguments and returns of type half">,
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MarshallingInfoFlag<LangOpts<"HalfArgsAndReturns">>,
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@ -3520,7 +3520,6 @@ static void RenderHLSLOptions(const ArgList &Args, ArgStringList &CmdArgs,
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// Add the default headers if dxc_no_stdinc is not set.
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if (!Args.hasArg(options::OPT_dxc_no_stdinc))
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CmdArgs.push_back("-finclude-default-header");
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CmdArgs.push_back("-fallow-half-arguments-and-returns");
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}
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static void RenderARCMigrateToolOptions(const Driver &D, const ArgList &Args,
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@ -12,4 +12,13 @@
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__attribute__((clang_builtin_alias(__builtin_hlsl_wave_active_count_bits))) uint
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WaveActiveCountBits(bool bBit);
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__attribute__((clang_builtin_alias(__builtin_abs))) int abs(int In);
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__attribute__((clang_builtin_alias(__builtin_labs))) int64_t abs(int64_t In);
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__attribute__((clang_builtin_alias(__builtin_fabsf))) float abs(float In);
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__attribute__((clang_builtin_alias(__builtin_fabs))) double abs(double In);
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#ifdef __HLSL_ENABLE_16_BIT
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__attribute__((clang_builtin_alias(__builtin_fabsf16))) half abs(half In);
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#endif
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#endif //_HLSL_HLSL_INTRINSICS_H_
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@ -0,0 +1,57 @@
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// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
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// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
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// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s
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// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -x hlsl -triple \
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// RUN: dxil-pc-shadermodel6.3-library %s -emit-llvm -disable-llvm-passes \
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// RUN: -o - | FileCheck %s --check-prefix=NO_HALF
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float abs_float(float X) {
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return abs(X);
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}
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// CHECK: define noundef float @"?abs_float@@YAMM@Z"(
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// CHECK: call float @llvm.fabs.f32(float %0)
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double abs_double(double X) {
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return abs(X);
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}
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// CHECK: define noundef double @"?abs_double@@YANN@Z"(
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// CHECK: call double @llvm.fabs.f64(double %0)
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half abs_half(half X) {
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return abs(X);
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}
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// CHECK: define noundef half @"?abs_half@@YA$f16@$f16@@Z"(
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// CHECK: call half @llvm.fabs.f16(half %0)
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// NO_HALF: define noundef float @"?abs_half@@YA$halff@$halff@@Z"(
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// NO_HALF: call float @llvm.fabs.f32(float %0)
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int abs_int(int X) {
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return abs(X);
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}
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// NO_HALF: define noundef i32 @"?abs_int@@YAHH@Z"(i32
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// CHECK: define noundef i32 @"?abs_int@@YAHH@Z"(i32
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// CHECK: [[A_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
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// CHECK-NEXT: [[NEG:%.*]] = sub nsw i32 0, [[TMP0]]
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// CHECK-NEXT: [[ABSCOND:%.*]] = icmp slt i32 [[TMP0]], 0
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// CHECK-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i32 [[NEG]], i32 [[TMP0]]
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// CHECK-NEXT: ret i32 [[ABS]]
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int64_t abs_int64(int64_t X) {
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return abs(X);
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}
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// CHECK: define noundef i64 @"?abs_int64@@YAJJ@Z"(i64
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// CHECK: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
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// CHECK-NEXT: [[NEG:%.*]] = sub nsw i64 0, [[TMP0]]
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// CHECK-NEXT: [[ABSCOND:%.*]] = icmp slt i64 [[TMP0]], 0
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// CHECK-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i64 [[NEG]], i64 [[TMP0]]
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// CHECK-NEXT: ret i64 [[ABS]]
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