forked from OSchip/llvm-project
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC
Treat this as legal on gfx9 since it can use S_PACK_* instructions for this. This isn't used by anything yet. The same will probably apply to 16-bit G_BUILD_VECTOR without the trunc. llvm-svn: 371423
This commit is contained in:
Matt Arsenault
parent
6d7fba6aae
commit
182f9248e8
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@ -719,6 +719,15 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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.legalIf(isRegisterType(0))
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.minScalarOrElt(0, S32);
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if (ST.hasScalarPackInsts()) {
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getActionDefinitionsBuilder(G_BUILD_VECTOR_TRUNC)
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.legalFor({V2S16, S32})
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.lower();
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} else {
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getActionDefinitionsBuilder(G_BUILD_VECTOR_TRUNC)
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.lower();
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}
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getActionDefinitionsBuilder(G_CONCAT_VECTORS)
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.legalIf(isRegisterType(0));
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@ -1305,6 +1305,44 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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MI.eraseFromParent();
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return;
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}
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case AMDGPU::G_BUILD_VECTOR_TRUNC: {
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assert(MI.getNumOperands() == 3 && empty(OpdMapper.getVRegs(0)));
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substituteSimpleCopyRegs(OpdMapper, 1);
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substituteSimpleCopyRegs(OpdMapper, 2);
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Register DstReg = MI.getOperand(0).getReg();
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const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
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if (DstBank == &AMDGPU::SGPRRegBank)
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break; // Can use S_PACK_* instructions.
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MachineIRBuilder B(MI);
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Register Lo = MI.getOperand(1).getReg();
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Register Hi = MI.getOperand(2).getReg();
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const RegisterBank *BankLo = getRegBank(Lo, MRI, *TRI);
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const RegisterBank *BankHi = getRegBank(Hi, MRI, *TRI);
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const LLT S32 = LLT::scalar(32);
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auto MaskLo = B.buildConstant(S32, 0xffff);
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MRI.setRegBank(MaskLo.getReg(0), *BankLo);
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auto ShiftAmt = B.buildConstant(S32, 16);
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MRI.setRegBank(ShiftAmt.getReg(0), *BankHi);
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auto ShiftHi = B.buildShl(S32, Hi, ShiftAmt);
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MRI.setRegBank(ShiftHi.getReg(0), *BankHi);
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auto Masked = B.buildAnd(S32, Lo, MaskLo);
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MRI.setRegBank(Masked.getReg(0), *BankLo);
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auto Or = B.buildOr(S32, Masked, ShiftHi);
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MRI.setRegBank(Or.getReg(0), *DstBank);
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B.buildBitcast(DstReg, Or);
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MI.eraseFromParent();
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return;
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}
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case AMDGPU::G_EXTRACT_VECTOR_ELT:
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applyDefaultMapping(OpdMapper);
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executeInWaterfallLoop(MI, MRI, { 2 });
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@ -1513,6 +1551,11 @@ AMDGPURegisterBankInfo::getRegBankID(Register Reg,
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return Bank ? Bank->getID() : Default;
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}
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static unsigned regBankUnion(unsigned RB0, unsigned RB1) {
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return (RB0 == AMDGPU::SGPRRegBankID && RB1 == AMDGPU::SGPRRegBankID) ?
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AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
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}
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///
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/// This function must return a legal mapping, because
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/// AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called
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@ -1774,6 +1817,20 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
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break;
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}
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case AMDGPU::G_BUILD_VECTOR_TRUNC: {
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assert(MI.getNumOperands() == 3);
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unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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unsigned Src0BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
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unsigned Src1BankID = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
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unsigned DstBankID = regBankUnion(Src0BankID, Src1BankID);
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OpdsMapping[0] = AMDGPU::getValueMapping(DstBankID, DstSize);
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OpdsMapping[1] = AMDGPU::getValueMapping(Src0BankID, SrcSize);
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OpdsMapping[2] = AMDGPU::getValueMapping(Src1BankID, SrcSize);
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break;
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}
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case AMDGPU::G_BITCAST:
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case AMDGPU::G_INTTOPTR:
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case AMDGPU::G_PTRTOINT:
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@ -551,6 +551,10 @@ public:
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return GFX9Insts;
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}
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bool hasScalarPackInsts() const {
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return GFX9Insts;
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}
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TrapHandlerAbi getTrapHandlerAbi() const {
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return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
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}
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@ -0,0 +1,19 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=GFX9 %s
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---
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name: legal_s32_to_v2s16
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX9-LABEL: name: legal_s32_to_v2s16
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; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
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; GFX9: S_NOP 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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S_NOP 0, implicit %2
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...
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@ -0,0 +1,83 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: build_vector_trunc_v2s16_s32_ss
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: build_vector_trunc_v2s16_s32_ss
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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...
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---
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name: build_vector_trunc_v2s16_s32_sv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: build_vector_trunc_v2s16_s32_sv
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 65535
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; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[COPY1]], [[C1]](s32)
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; CHECK: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[AND]], [[SHL]]
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; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[OR]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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...
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---
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name: build_vector_trunc_v2s16_s32_vs
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: build_vector_trunc_v2s16_s32_vs
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 65535
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY1]], [[C1]](s32)
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; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[AND]], [[SHL]]
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; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[OR]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $sgpr0
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%2:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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...
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---
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name: build_vector_trunc_v2s16_s32_vv
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: build_vector_trunc_v2s16_s32_vv
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 65535
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; CHECK: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 16
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; CHECK: [[SHL:%[0-9]+]]:vgpr(s32) = G_SHL [[COPY1]], [[C1]](s32)
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; CHECK: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]
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; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[AND]], [[SHL]]
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; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[OR]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
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...
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