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Tidy up a bit. 

llvm-svn: 145458
This commit is contained in:
Jim Grosbach 2011-11-29 23:51:09 +00:00
parent 187748456a
commit 182b6a077e
2 changed files with 10 additions and 33 deletions
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5
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -78,6 +78,7 @@ def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
def VecListOneDAsmOperand : AsmOperandClass {
let Name = "VecListOneD";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListOperands";
}
def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
let ParserMatchClass = VecListOneDAsmOperand;
@ -86,6 +87,7 @@ def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
def VecListTwoDAsmOperand : AsmOperandClass {
let Name = "VecListTwoD";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListOperands";
}
def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
let ParserMatchClass = VecListTwoDAsmOperand;
@ -94,6 +96,7 @@ def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
def VecListThreeDAsmOperand : AsmOperandClass {
let Name = "VecListThreeD";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListOperands";
}
def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
let ParserMatchClass = VecListThreeDAsmOperand;
@ -102,6 +105,7 @@ def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
def VecListFourDAsmOperand : AsmOperandClass {
let Name = "VecListFourD";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListOperands";
}
def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
let ParserMatchClass = VecListFourDAsmOperand;
@ -110,6 +114,7 @@ def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
def VecListTwoQAsmOperand : AsmOperandClass {
let Name = "VecListTwoQ";
let ParserMethod = "parseVectorList";
let RenderMethod = "addVecListOperands";
}
def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwo"> {
let ParserMatchClass = VecListTwoQAsmOperand;

38
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -1527,39 +1527,11 @@ public:
Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
}
void addVecListOneDOperands(MCInst &Inst, unsigned N) const {
void addVecListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVecListTwoDOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Only the first register actually goes on the instruction. The rest
// are implied by the opcode.
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVecListThreeDOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Only the first register actually goes on the instruction. The rest
// are implied by the opcode.
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVecListFourDOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Only the first register actually goes on the instruction. The rest
// are implied by the opcode.
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVecListTwoQOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// Only the first register actually goes on the instruction. The rest
// are implied by the opcode.
Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
}
void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
@ -3444,7 +3416,7 @@ bool ARMAsmParser::
cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Vd
((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// Vn
@ -3458,7 +3430,7 @@ bool ARMAsmParser::
cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
// Vd
((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
// Create a writeback register dummy placeholder.
Inst.addOperand(MCOperand::CreateImm(0));
// Vn
@ -3478,7 +3450,7 @@ cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
// Vn
((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
// Vt
((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
return true;
@ -3494,7 +3466,7 @@ cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
// Vm
((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
// Vt
((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
// pred
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
return true;