forked from OSchip/llvm-project
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b4fd2c90e9
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@ -316,11 +316,11 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def tBRIND : TI<(outs), (ins GPR:$Rm), IIC_Br, "mov\tpc, $Rm",
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[(brind GPR:$Rm)]>,
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T1Special<{1,0,1,?}> {
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T1Special<{1,0,?,?}> {
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bits<4> Rm;
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let Inst{6-3} = Rm;
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let Inst{2-0} = 0b111; // <Rd> = Inst{7:2-0} = pc
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let Inst{7} = 0b1; // <Rd> = Inst{7:2-0} = pc
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let Inst{2-0} = 0b111;
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}
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}
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@ -332,7 +332,6 @@ def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
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"pop${p}\t$regs", []>,
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T1Misc<{1,1,0,?,?,?,?}> {
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bits<16> regs;
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let Inst{8} = regs{15};
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let Inst{7-0} = regs{7-0};
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}
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@ -442,13 +441,25 @@ let isBranch = 1, isTerminator = 1 in
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// Compare and branch on zero / non-zero
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let isBranch = 1, isTerminator = 1 in {
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def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
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"cbz\t$cmp, $target", []>,
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T1Misc<{0,0,?,1,?,?,?}>;
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def tCBZ : T1I<(outs), (ins tGPR:$Rn, brtarget:$target), IIC_Br,
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"cbz\t$Rn, $target", []>,
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T1Misc<{0,0,?,1,?,?,?}> {
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bits<6> target;
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bits<3> Rn;
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let Inst{9} = target{5};
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let Inst{7-3} = target{4-0};
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let Inst{2-0} = Rn;
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}
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def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
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"cbnz\t$cmp, $target", []>,
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T1Misc<{1,0,?,1,?,?,?}>;
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T1Misc<{1,0,?,1,?,?,?}> {
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bits<6> target;
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bits<3> Rn;
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let Inst{9} = target{5};
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let Inst{7-3} = target{4-0};
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let Inst{2-0} = Rn;
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}
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}
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// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
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