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[AMDGPU] Assert in getOpSize() there are no sub-dword subregs 

Differential Revision: https://reviews.llvm.org/D52769

llvm-svn: 343648
This commit is contained in:
Stanislav Mekhanoshin 2018-10-03 00:00:41 +00:00
parent b02ba99e91
commit 1821513e2f
1 changed files with 6 additions and 1 deletions
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7
llvm/lib/Target/AMDGPU/SIInstrInfo.h
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@ -732,8 +732,13 @@ public:
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
const MachineOperand &MO = MI.getOperand(OpNo);
if (MO.isReg()) {
if (unsigned SubReg = MO.getSubReg())
if (unsigned SubReg = MO.getSubReg()) {
assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
MI.getParent()->getParent()->getRegInfo().
getRegClass(MO.getReg()), SubReg)) >= 32 &&
"Sub-dword subregs are not supported");
return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
}
}
return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
}