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[x86] add more tests for signbit math; NFC 

llvm-svn: 338131
This commit is contained in:
Sanjay Patel 2018-07-27 16:22:40 +00:00
parent 60c04b961e
commit 1812d33e22
1 changed files with 84 additions and 0 deletions
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84
llvm/test/CodeGen/X86/signbit-shift.ll
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@ -29,6 +29,20 @@ define i32 @add_zext_ifpos(i32 %x) {
ret i32 %r ret i32 %r
} }
define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_zext_ifpos_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
; CHECK-NEXT: psrld $31, %xmm0
; CHECK-NEXT: por {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = zext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r
}
define i32 @sel_ifpos_tval_bigger(i32 %x) { define i32 @sel_ifpos_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_tval_bigger: ; CHECK-LABEL: sel_ifpos_tval_bigger:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
@ -68,6 +82,19 @@ define i32 @add_sext_ifpos(i32 %x) {
ret i32 %r ret i32 %r
} }
define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_sext_ifpos_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pcmpgtd %xmm1, %xmm0
; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
%c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = sext <4 x i1> %c to <4 x i32>
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r
}
define i32 @sel_ifpos_fval_bigger(i32 %x) { define i32 @sel_ifpos_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_fval_bigger: ; CHECK-LABEL: sel_ifpos_fval_bigger:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
@ -155,3 +182,60 @@ define i32 @sel_ifneg_fval_bigger(i32 %x) {
ret i32 %r ret i32 %r
} }
define i32 @add_lshr_not(i32 %x) {
; CHECK-LABEL: add_lshr_not:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: notl %edi
; CHECK-NEXT: shrl $31, %edi
; CHECK-NEXT: leal 41(%rdi), %eax
; CHECK-NEXT: retq
%not = xor i32 %x, -1
%sh = lshr i32 %not, 31
%r = add i32 %sh, 41
ret i32 %r
}
define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: add_lshr_not_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: psrld $31, %xmm0
; CHECK-NEXT: por {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r
}
define i32 @sub_lshr_not(i32 %x) {
; CHECK-LABEL: sub_lshr_not:
; CHECK: # %bb.0:
; CHECK-NEXT: notl %edi
; CHECK-NEXT: shrl $31, %edi
; CHECK-NEXT: xorl $43, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%not = xor i32 %x, -1
%sh = lshr i32 %not, 31
%r = sub i32 43, %sh
ret i32 %r
}
define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {
; CHECK-LABEL: sub_lshr_not_vec_splat:
; CHECK: # %bb.0:
; CHECK-NEXT: pcmpeqd %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm0, %xmm1
; CHECK-NEXT: psrld $31, %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [42,42,42,42]
; CHECK-NEXT: psubd %xmm1, %xmm0
; CHECK-NEXT: retq
%c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
%e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>
%r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e
ret <4 x i32> %r
}