forked from OSchip/llvm-project
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
This reverts commit 0345d88de6
.
Google internal backend uses EntrySU, we are looking into removing
dependency on it.
Differential Revision: https://reviews.llvm.org/D88018
This commit is contained in:
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af29591650
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17dc729bd4
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@ -234,7 +234,7 @@ public:
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virtual void leaveMBB() {};
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/// Notify this strategy that all roots have been released (including those
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/// that depend on ExitSU).
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/// that depend on EntrySU or ExitSU).
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virtual void registerRoots() {}
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/// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
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@ -560,6 +560,7 @@ class TargetRegisterInfo;
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MachineFunction &MF; ///< Machine function
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MachineRegisterInfo &MRI; ///< Virtual/real register map
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std::vector<SUnit> SUnits; ///< The scheduling units.
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SUnit EntrySU; ///< Special node for the region entry.
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SUnit ExitSU; ///< Special node for the region exit.
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#ifdef NDEBUG
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@ -680,7 +680,7 @@ void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
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PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency();
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--PredSU->NumSuccsLeft;
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if (PredSU->NumSuccsLeft == 0)
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if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU)
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SchedImpl->releaseBottomNode(PredSU);
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}
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@ -853,7 +853,7 @@ void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
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NextClusterSucc = nullptr;
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NextClusterPred = nullptr;
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// Release all DAG roots for scheduling, not including ExitSU.
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// Release all DAG roots for scheduling, not including EntrySU/ExitSU.
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//
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// Nodes with unreleased weak edges can still be roots.
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// Release top roots in forward order.
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@ -867,6 +867,7 @@ void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots,
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SchedImpl->releaseBottomNode(*I);
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}
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releaseSuccessors(&EntrySU);
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releasePredecessors(&ExitSU);
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SchedImpl->registerRoots();
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@ -1167,6 +1168,8 @@ void ScheduleDAGMILive::updatePressureDiffs(
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void ScheduleDAGMILive::dump() const {
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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if (EntrySU.getInstr() != nullptr)
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dumpNodeAll(EntrySU);
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for (const SUnit &SU : SUnits) {
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dumpNodeAll(SU);
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if (ShouldTrackPressure) {
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@ -109,21 +109,23 @@ static bool fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU,
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// Make the FirstSU also dependent on the dependencies of the SecondSU to
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// prevent them from being scheduled between the FirstSU and the SecondSU.
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for (const SDep &SI : SecondSU.Preds) {
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SUnit *SU = SI.getSUnit();
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if (SI.isWeak() || isHazard(SI) || &FirstSU == SU || FirstSU.isSucc(SU))
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continue;
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LLVM_DEBUG(dbgs() << " Bind "; DAG.dumpNodeName(*SU); dbgs() << " - ";
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DAG.dumpNodeName(FirstSU); dbgs() << '\n';);
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DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial));
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}
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// ExitSU comes last by design, which acts like an implicit dependency
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// between ExitSU and any bottom root in the graph. We should transfer
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// this to FirstSU as well.
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if (&SecondSU == &DAG.ExitSU) {
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for (SUnit &SU : DAG.SUnits) {
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if (SU.Succs.empty())
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DAG.addEdge(&FirstSU, SDep(&SU, SDep::Artificial));
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if (&FirstSU != &DAG.EntrySU) {
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for (const SDep &SI : SecondSU.Preds) {
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SUnit *SU = SI.getSUnit();
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if (SI.isWeak() || isHazard(SI) || &FirstSU == SU || FirstSU.isSucc(SU))
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continue;
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LLVM_DEBUG(dbgs() << " Bind "; DAG.dumpNodeName(*SU); dbgs() << " - ";
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DAG.dumpNodeName(FirstSU); dbgs() << '\n';);
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DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial));
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}
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// ExitSU comes last by design, which acts like an implicit dependency
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// between ExitSU and any bottom root in the graph. We should transfer
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// this to FirstSU as well.
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if (&SecondSU == &DAG.ExitSU) {
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for (SUnit &SU : DAG.SUnits) {
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if (SU.Succs.empty())
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DAG.addEdge(&FirstSU, SDep(&SU, SDep::Artificial));
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}
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}
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}
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@ -527,6 +527,9 @@ void SchedulePostRATDList::ListScheduleTopDown() {
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// blocks are a single region).
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HazardRec->Reset();
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// Release any successors of the special Entry node.
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ReleaseSuccessors(&EntrySU);
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// Add all leaves to Available queue.
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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// It is available if it has no predecessors.
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@ -63,6 +63,7 @@ ScheduleDAG::~ScheduleDAG() = default;
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void ScheduleDAG::clearDAG() {
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SUnits.clear();
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EntrySU = SUnit();
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ExitSU = SUnit();
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}
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@ -351,7 +352,9 @@ LLVM_DUMP_METHOD void SUnit::dumpAttributes() const {
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}
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LLVM_DUMP_METHOD void ScheduleDAG::dumpNodeName(const SUnit &SU) const {
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if (&SU == &ExitSU)
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if (&SU == &EntrySU)
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dbgs() << "EntrySU";
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else if (&SU == &ExitSU)
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dbgs() << "ExitSU";
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else
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dbgs() << "SU(" << SU.NodeNum << ")";
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@ -653,7 +656,7 @@ std::vector<int> ScheduleDAGTopologicalSort::GetSubGraph(const SUnit &StartSU,
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for (int I = SU->Preds.size()-1; I >= 0; --I) {
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const SUnit *Pred = SU->Preds[I].getSUnit();
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unsigned s = Pred->NodeNum;
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// Edges to non-SUnits are allowed but ignored (e.g. ExitSU).
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// Edges to non-SUnits are allowed but ignored (e.g. EntrySU).
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if (Pred->isBoundaryNode())
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continue;
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if (Node2Index[s] == LowerBound) {
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@ -1167,6 +1167,8 @@ void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const {
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void ScheduleDAGInstrs::dump() const {
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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if (EntrySU.getInstr() != nullptr)
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dumpNodeAll(EntrySU);
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for (const SUnit &SU : SUnits)
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dumpNodeAll(SU);
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if (ExitSU.getInstr() != nullptr)
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@ -1177,7 +1179,9 @@ void ScheduleDAGInstrs::dump() const {
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std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
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std::string s;
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raw_string_ostream oss(s);
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if (SU == &ExitSU)
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if (SU == &EntrySU)
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oss << "<entry>";
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else if (SU == &ExitSU)
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oss << "<exit>";
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else
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SU->getInstr()->print(oss, /*IsStandalone=*/true);
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@ -150,8 +150,8 @@ void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) {
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--PredSU->NumSuccsLeft;
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// If all the node's successors are scheduled, this node is ready
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// to be scheduled.
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if (PredSU->NumSuccsLeft == 0) {
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// to be scheduled. Ignore the special EntrySU node.
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if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
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PredSU->isAvailable = true;
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AvailableQueue.push(PredSU);
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}
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@ -415,8 +415,8 @@ void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) {
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}
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// If all the node's successors are scheduled, this node is ready
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// to be scheduled.
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if (PredSU->NumSuccsLeft == 0) {
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// to be scheduled. Ignore the special EntrySU node.
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if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) {
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PredSU->isAvailable = true;
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unsigned Height = PredSU->getHeight();
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@ -696,6 +696,8 @@ void ScheduleDAGSDNodes::dumpNode(const SUnit &SU) const {
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void ScheduleDAGSDNodes::dump() const {
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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if (EntrySU.getNode() != nullptr)
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dumpNodeAll(EntrySU);
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for (const SUnit &SU : SUnits)
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dumpNodeAll(SU);
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if (ExitSU.getNode() != nullptr)
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@ -166,6 +166,9 @@ void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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void ScheduleDAGVLIW::listScheduleTopDown() {
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unsigned CurCycle = 0;
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// Release any successors of the special Entry node.
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releaseSuccessors(&EntrySU);
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// All leaves to AvailableQueue.
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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// It is available if it has no predecessors.
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@ -248,6 +248,7 @@ GCNMinRegScheduler::schedule(ArrayRef<const SUnit*> TopRoots,
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for (auto SU : TopRoots) {
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RQ.push_back(*new (Alloc.Allocate()) Candidate(SU, StepNo));
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}
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releaseSuccessors(&DAG.EntrySU, StepNo);
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while (!RQ.empty()) {
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LLVM_DEBUG(dbgs() << "\n=== Picking candidate, Step = " << StepNo
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@ -455,6 +455,7 @@ public:
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MachineRegisterInfo *getMRI() { return &MRI; }
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const TargetRegisterInfo *getTRI() { return TRI; }
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ScheduleDAGTopologicalSort *GetTopo() { return &Topo; }
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SUnit &getEntrySU() { return EntrySU; }
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SUnit& getExitSU() { return ExitSU; }
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void restoreSULinksLeft();
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