forked from OSchip/llvm-project
Move CaseBlock, JumpTable, and BitTestBlock to be members of
SelectionDAGLowering instead of being in an anonymous namespace. This fixes warnings about SelectionDAGLowering having fields using anonymous namespaces. llvm-svn: 55497
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360c57f683
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@ -523,84 +523,6 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
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return FirstReg;
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}
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namespace {
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/// CaseBlock - This structure is used to communicate between SDLowering and
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/// SDISel for the code generation of additional basic blocks needed by multi-
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/// case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
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MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
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MachineBasicBlock *me)
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: CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
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// Emit by default LHS op RHS. MHS is used for range comparisons:
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// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
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Value *CmpLHS, *CmpMHS, *CmpRHS;
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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// ThisBB - the block into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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};
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struct JumpTable {
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JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
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MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
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/// Reg - the virtual register containing the index of the jump table entry
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//. to jump to.
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unsigned Reg;
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/// JTI - the JumpTableIndex for this jump table in the function.
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unsigned JTI;
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/// MBB - the MBB into which to emit the code for the indirect jump.
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MachineBasicBlock *MBB;
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/// Default - the MBB of the default bb, which is a successor of the range
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/// check MBB. This is when updating PHI nodes in successors.
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MachineBasicBlock *Default;
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};
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struct JumpTableHeader {
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JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
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bool E = false):
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First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
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uint64_t First;
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uint64_t Last;
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Value *SValue;
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MachineBasicBlock *HeaderBB;
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bool Emitted;
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};
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typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
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struct BitTestCase {
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BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
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Mask(M), ThisBB(T), TargetBB(Tr) { }
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uint64_t Mask;
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MachineBasicBlock* ThisBB;
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MachineBasicBlock* TargetBB;
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};
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typedef SmallVector<BitTestCase, 3> BitTestInfo;
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struct BitTestBlock {
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BitTestBlock(uint64_t F, uint64_t R, Value* SV,
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unsigned Rg, bool E,
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MachineBasicBlock* P, MachineBasicBlock* D,
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const BitTestInfo& C):
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First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
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Parent(P), Default(D), Cases(C) { }
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uint64_t First;
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uint64_t Range;
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Value *SValue;
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unsigned Reg;
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bool Emitted;
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MachineBasicBlock *Parent;
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MachineBasicBlock *Default;
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BitTestInfo Cases;
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};
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} // end anonymous namespace
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//===----------------------------------------------------------------------===//
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/// SelectionDAGLowering - This is the common target-independent lowering
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/// implementation that is parameterized by a TargetLowering object.
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@ -694,6 +616,80 @@ class SelectionDAGLowering {
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unsigned Clusterify(CaseVector& Cases, const SwitchInst &SI);
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/// CaseBlock - This structure is used to communicate between SDLowering and
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/// SDISel for the code generation of additional basic blocks needed by multi-
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/// case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, Value *cmplhs, Value *cmprhs, Value *cmpmiddle,
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MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
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MachineBasicBlock *me)
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: CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me) {}
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
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// Emit by default LHS op RHS. MHS is used for range comparisons:
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// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
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Value *CmpLHS, *CmpMHS, *CmpRHS;
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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// ThisBB - the block into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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};
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struct JumpTable {
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JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
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MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
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/// Reg - the virtual register containing the index of the jump table entry
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//. to jump to.
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unsigned Reg;
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/// JTI - the JumpTableIndex for this jump table in the function.
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unsigned JTI;
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/// MBB - the MBB into which to emit the code for the indirect jump.
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MachineBasicBlock *MBB;
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/// Default - the MBB of the default bb, which is a successor of the range
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/// check MBB. This is when updating PHI nodes in successors.
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MachineBasicBlock *Default;
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};
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struct JumpTableHeader {
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JumpTableHeader(uint64_t F, uint64_t L, Value* SV, MachineBasicBlock* H,
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bool E = false):
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First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
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uint64_t First;
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uint64_t Last;
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Value *SValue;
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MachineBasicBlock *HeaderBB;
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bool Emitted;
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};
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typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
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struct BitTestCase {
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BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
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Mask(M), ThisBB(T), TargetBB(Tr) { }
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uint64_t Mask;
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MachineBasicBlock* ThisBB;
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MachineBasicBlock* TargetBB;
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};
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typedef SmallVector<BitTestCase, 3> BitTestInfo;
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struct BitTestBlock {
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BitTestBlock(uint64_t F, uint64_t R, Value* SV,
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unsigned Rg, bool E,
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MachineBasicBlock* P, MachineBasicBlock* D,
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const BitTestInfo& C):
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First(F), Range(R), SValue(SV), Reg(Rg), Emitted(E),
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Parent(P), Default(D), Cases(C) { }
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uint64_t First;
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uint64_t Range;
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Value *SValue;
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unsigned Reg;
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bool Emitted;
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MachineBasicBlock *Parent;
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MachineBasicBlock *Default;
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BitTestInfo Cases;
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};
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public:
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// TLI - This is information that describes the available target features we
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// need for lowering. This indicates when operations are unavailable,
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@ -839,6 +835,7 @@ public:
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void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
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unsigned Opc);
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bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
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bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
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void ExportFromCurrentBlock(Value *V);
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void LowerCallTo(CallSite CS, SDValue Callee, bool IsTailCall,
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@ -1618,8 +1615,8 @@ void SelectionDAGLowering::FindMergedConditions(Value *Cond,
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/// If the set of cases should be emitted as a series of branches, return true.
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/// If we should emit this as a bunch of and/or'd together conditions, return
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/// false.
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static bool
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ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
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bool
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SelectionDAGLowering::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
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if (Cases.size() != 2) return true;
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// If this is two comparisons of the same values or'd or and'd together, they
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