forked from OSchip/llvm-project
parent
56b34f6c51
commit
17ba6becaa
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@ -26,7 +26,7 @@ multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
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"v128.const\t"#args, 0>;
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}
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multiclass SIMDLoad<ValueType vec_t> {
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let mayLoad = 1, isAsCheapAsAMove = 1 in
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let mayLoad = 1 in
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defm LOAD_#vec_t :
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SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
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(outs), (ins P2Align:$align, offset32_op:$off), [],
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@ -34,7 +34,7 @@ multiclass SIMDLoad<ValueType vec_t> {
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"v128.load\t$off$align", 1>;
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}
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multiclass SIMDStore<ValueType vec_t> {
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let mayStore = 1, isAsCheapAsAMove = 1 in
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let mayStore = 1 in
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defm STORE_#vec_t :
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SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
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(outs), (ins P2Align:$align, offset32_op:$off), [],
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