forked from OSchip/llvm-project
Revert "[llvm][CodeGen] Addressing modes for SVE stN."
This reverts commit fc4e954ed5.
The commit reported the following failure:
http://lab.llvm.org:8011/builders/clang-armv7-linux-build-cache/builds/29420
FAILED: lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64ISelDAGToDAG.cpp.o
/usr/bin/c++ -DGTEST_HAS_RTTI=0 -D_DEBUG -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGEFILE_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Ilib/Target/AArch64 -I/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/Target/AArch64 -I/usr/include/libxml2 -Iinclude -I/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/include -mthumb -fPIC -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -fdiagnostics-color -ffunction-sections -fdata-sections -O3 -fvisibility=hidden -fno-exceptions -fno-rtti -UNDEBUG -std=c++14 -MMD -MT lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64ISelDAGToDAG.cpp.o -MF lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64ISelDAGToDAG.cpp.o.d -o lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64ISelDAGToDAG.cpp.o -c /home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
/home/buildslave/buildslave/clang-armv7-linux-build-cache/llvm/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1439:10: error: chosen constructor is explicit in copy-initialization
return {IsRegReg ? Opc_rr : Opc_ri, NewBase, NewOffset};
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/bin/../lib/gcc/arm-linux-gnueabihf/5.4.0/../../../../include/c++/5.4.0/tuple:479:19: note: explicit constructor declared here
constexpr tuple(_UElements&&... __elements)
This commit is contained in:
Francesco Petrogalli
parent
992fbce4e9
commit
17b1869b72
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@ -261,14 +261,7 @@ public:
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void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
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void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
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template <unsigned Scale>
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void SelectPredicatedStore(SDNode *N, unsigned NumVecs, const unsigned Opc_rr,
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const unsigned Opc_ri);
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template <unsigned Scale>
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std::tuple<unsigned, SDValue, SDValue>
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findAddrModeSVELoadStore(SDNode *N, const unsigned Opc_rr,
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const unsigned Opc_ri, const SDValue &OldBase,
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const SDValue &OldOffset);
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void SelectPredicatedStore(SDNode *N, unsigned NumVecs, const unsigned Opc);
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bool tryBitfieldExtractOp(SDNode *N);
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bool tryBitfieldExtractOpFromSExt(SDNode *N);
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@ -1415,30 +1408,6 @@ void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
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CurDAG->RemoveDeadNode(N);
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}
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/// Optimize \param OldBase and \param OldOffset selecting the best addressing
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/// mode. Returns a tuple consisting of an Opcode, an SDValue representing the
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/// new Base and an SDValue representing the new offset.
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template <unsigned Scale>
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std::tuple<unsigned, SDValue, SDValue>
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AArch64DAGToDAGISel::findAddrModeSVELoadStore(SDNode *N, const unsigned Opc_rr,
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const unsigned Opc_ri,
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const SDValue &OldBase,
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const SDValue &OldOffset) {
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SDValue NewBase = OldBase;
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SDValue NewOffset = OldOffset;
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// Detect a possible Reg+Imm addressing mode.
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const bool IsRegImm = SelectAddrModeIndexedSVE</*Min=*/-8, /*Max=*/7>(
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N, OldBase, NewBase, NewOffset);
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// Detect a possible reg+reg addressing mode, but only if we haven't already
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// detected a Reg+Imm one.
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const bool IsRegReg =
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!IsRegImm && SelectSVERegRegAddrMode<Scale>(OldBase, NewBase, NewOffset);
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// Select the instruction.
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return {IsRegReg ? Opc_rr : Opc_ri, NewBase, NewOffset};
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}
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void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
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unsigned Opc) {
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SDLoc dl(N);
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@ -1459,27 +1428,18 @@ void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
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ReplaceNode(N, St);
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}
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template <unsigned Scale>
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void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs,
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const unsigned Opc_rr,
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const unsigned Opc_ri) {
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const unsigned Opc) {
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SDLoc dl(N);
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// Form a REG_SEQUENCE to force register allocation.
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SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
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SDValue RegSeq = createZTuple(Regs);
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// Optimize addressing mode.
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unsigned Opc;
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SDValue Offset, Base;
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std::tie(Opc, Base, Offset) = findAddrModeSVELoadStore<Scale>(
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N, Opc_rr, Opc_ri, N->getOperand(NumVecs + 3),
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CurDAG->getTargetConstant(0, dl, MVT::i64));
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SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate
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Base, // address
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Offset, // offset
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N->getOperand(0)}; // chain
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SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), // predicate
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N->getOperand(NumVecs + 3), // address
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CurDAG->getTargetConstant(0, dl, MVT::i64), // offset
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N->getOperand(0)}; // chain
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SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
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ReplaceNode(N, St);
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@ -3950,60 +3910,48 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
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}
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case Intrinsic::aarch64_sve_st2: {
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if (VT == MVT::nxv16i8) {
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SelectPredicatedStore</*Scale=*/0>(Node, 2, AArch64::ST2B,
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AArch64::ST2B_IMM);
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SelectPredicatedStore(Node, 2, AArch64::ST2B_IMM);
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return;
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} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16) {
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SelectPredicatedStore</*Scale=*/1>(Node, 2, AArch64::ST2H,
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AArch64::ST2H_IMM);
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SelectPredicatedStore(Node, 2, AArch64::ST2H_IMM);
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return;
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} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
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SelectPredicatedStore</*Scale=*/2>(Node, 2, AArch64::ST2W,
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AArch64::ST2W_IMM);
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SelectPredicatedStore(Node, 2, AArch64::ST2W_IMM);
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return;
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} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
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SelectPredicatedStore</*Scale=*/3>(Node, 2, AArch64::ST2D,
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AArch64::ST2D_IMM);
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SelectPredicatedStore(Node, 2, AArch64::ST2D_IMM);
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return;
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}
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break;
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}
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case Intrinsic::aarch64_sve_st3: {
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if (VT == MVT::nxv16i8) {
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SelectPredicatedStore</*Scale=*/0>(Node, 3, AArch64::ST3B,
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AArch64::ST3B_IMM);
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SelectPredicatedStore(Node, 3, AArch64::ST3B_IMM);
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return;
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} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16) {
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SelectPredicatedStore</*Scale=*/1>(Node, 3, AArch64::ST3H,
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AArch64::ST3H_IMM);
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SelectPredicatedStore(Node, 3, AArch64::ST3H_IMM);
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return;
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} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
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SelectPredicatedStore</*Scale=*/2>(Node, 3, AArch64::ST3W,
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AArch64::ST3W_IMM);
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SelectPredicatedStore(Node, 3, AArch64::ST3W_IMM);
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return;
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} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
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SelectPredicatedStore</*Scale=*/3>(Node, 3, AArch64::ST3D,
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AArch64::ST3D_IMM);
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SelectPredicatedStore(Node, 3, AArch64::ST3D_IMM);
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return;
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}
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break;
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}
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case Intrinsic::aarch64_sve_st4: {
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if (VT == MVT::nxv16i8) {
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SelectPredicatedStore</*Scale=*/0>(Node, 4, AArch64::ST4B,
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AArch64::ST4B_IMM);
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SelectPredicatedStore(Node, 4, AArch64::ST4B_IMM);
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return;
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} else if (VT == MVT::nxv8i16 || VT == MVT::nxv8f16) {
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SelectPredicatedStore</*Scale=*/1>(Node, 4, AArch64::ST4H,
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AArch64::ST4H_IMM);
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SelectPredicatedStore(Node, 4, AArch64::ST4H_IMM);
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return;
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} else if (VT == MVT::nxv4i32 || VT == MVT::nxv4f32) {
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SelectPredicatedStore</*Scale=*/2>(Node, 4, AArch64::ST4W,
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AArch64::ST4W_IMM);
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SelectPredicatedStore(Node, 4, AArch64::ST4W_IMM);
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return;
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} else if (VT == MVT::nxv2i64 || VT == MVT::nxv2f64) {
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SelectPredicatedStore</*Scale=*/3>(Node, 4, AArch64::ST4D,
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AArch64::ST4D_IMM);
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SelectPredicatedStore(Node, 4, AArch64::ST4D_IMM);
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return;
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}
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break;
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@ -4639,9 +4587,6 @@ static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
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if (isa<MemSDNode>(Root))
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return cast<MemSDNode>(Root)->getMemoryVT();
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if (isa<MemIntrinsicSDNode>(Root))
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return cast<MemIntrinsicSDNode>(Root)->getMemoryVT();
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const unsigned Opcode = Root->getOpcode();
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// For custom ISD nodes, we have to look at them individually to extract the
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// type of the data moved to/from memory.
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@ -8913,30 +8913,6 @@ SDValue AArch64TargetLowering::LowerVSCALE(SDValue Op,
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DL, VT);
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}
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/// Set the IntrinsicInfo for the `aarch64_sve_st<N>` intrinsics.
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template <unsigned NumVecs>
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static bool setInfoSVEStN(AArch64TargetLowering::IntrinsicInfo &Info,
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const CallInst &CI) {
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Info.opc = ISD::INTRINSIC_VOID;
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// Retrieve EC from first vector argument.
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const EVT VT = EVT::getEVT(CI.getArgOperand(0)->getType());
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ElementCount EC = VT.getVectorElementCount();
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#ifndef NDEBUG
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// Check the assumption that all input vectors are the same type.
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for (unsigned I = 0; I < NumVecs; ++I)
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assert(VT == EVT::getEVT(CI.getArgOperand(I)->getType()) &&
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"Invalid type.");
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#endif
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// memVT is `NumVecs * VT`.
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Info.memVT = EVT::getVectorVT(CI.getType()->getContext(), VT.getScalarType(),
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EC * NumVecs);
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Info.ptrVal = CI.getArgOperand(CI.getNumArgOperands() - 1);
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Info.offset = 0;
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Info.align.reset();
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Info.flags = MachineMemOperand::MOStore;
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return true;
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}
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/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
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/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
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/// specified in the intrinsic calls.
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@ -8946,12 +8922,6 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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unsigned Intrinsic) const {
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auto &DL = I.getModule()->getDataLayout();
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switch (Intrinsic) {
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case Intrinsic::aarch64_sve_st2:
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return setInfoSVEStN<2>(Info, I);
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case Intrinsic::aarch64_sve_st3:
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return setInfoSVEStN<3>(Info, I);
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case Intrinsic::aarch64_sve_st4:
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return setInfoSVEStN<4>(Info, I);
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case Intrinsic::aarch64_neon_ld2:
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case Intrinsic::aarch64_neon_ld3:
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case Intrinsic::aarch64_neon_ld4:
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@ -1,614 +0,0 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
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; NOTE: invalid, upper and lower bound immediate values of the reg+imm
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; addressing mode are checked only for the byte version of each
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; instruction (`st<N>b`), as the code for detecting the immediate is
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; common to all instructions, and varies only for the number of
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; elements of the structured store, which is <N> = 2, 3, 4.
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;
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; ST2B
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;
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define void @st2b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: st2b_i8_valid_imm:
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; CHECK: st2b { z0.b, z1.b }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 2
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call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
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<vscale x 16 x i8> %v1,
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<vscale x 16 x i1> %pred,
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<vscale x 16 x i8>* %base)
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ret void
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}
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define void @st2b_i8_invalid_imm_not_multiple_of_2(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: st2b_i8_invalid_imm_not_multiple_of_2:
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; CHECK: rdvl x[[N:[0-9]+]], #3
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; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x[[N]]]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 3
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call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
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<vscale x 16 x i8> %v1,
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<vscale x 16 x i1> %pred,
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<vscale x 16 x i8>* %base)
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ret void
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}
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define void @st2b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: st2b_i8_invalid_imm_out_of_lower_bound:
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; CHECK: rdvl x[[N:[0-9]+]], #-18
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; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x[[N]]]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -18
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call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
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<vscale x 16 x i8> %v1,
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<vscale x 16 x i1> %pred,
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<vscale x 16 x i8>* %base)
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ret void
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}
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define void @st2b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: st2b_i8_invalid_imm_out_of_upper_bound:
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; CHECK: rdvl x[[N:[0-9]+]], #16
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; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x[[N]]]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 16
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call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
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<vscale x 16 x i8> %v1,
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<vscale x 16 x i1> %pred,
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<vscale x 16 x i8>* %base)
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ret void
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}
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define void @st2b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: st2b_i8_valid_imm_lower_bound:
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; CHECK: st2b { z0.b, z1.b }, p0, [x0, #-16, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -16
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call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
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<vscale x 16 x i8> %v1,
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<vscale x 16 x i1> %pred,
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<vscale x 16 x i8>* %base)
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ret void
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}
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define void @st2b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: st2b_i8_valid_imm_upper_bound:
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; CHECK: st2b { z0.b, z1.b }, p0, [x0, #14, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 14
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call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
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<vscale x 16 x i8> %v1,
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<vscale x 16 x i1> %pred,
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<vscale x 16 x i8>* %base)
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ret void
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}
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;
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; ST2H
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;
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define void @st2h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
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; CHECK-LABEL: st2h_i16:
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; CHECK: st2h { z0.h, z1.h }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: ret
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%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 2
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call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0,
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<vscale x 8 x i16> %v1,
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<vscale x 8 x i1> %pred,
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<vscale x 8 x i16>* %base)
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ret void
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}
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|
||||
define void @st2h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
|
||||
; CHECK-LABEL: st2h_f16:
|
||||
; CHECK: st2h { z0.h, z1.h }, p0, [x0, #2, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 2
|
||||
call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0,
|
||||
<vscale x 8 x half> %v1,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x half>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST2W
|
||||
;
|
||||
|
||||
define void @st2w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
|
||||
; CHECK-LABEL: st2w_i32:
|
||||
; CHECK: st2w { z0.s, z1.s }, p0, [x0, #4, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 4
|
||||
call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0,
|
||||
<vscale x 4 x i32> %v1,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x i32>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st2w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
|
||||
; CHECK-LABEL: st2w_f32:
|
||||
; CHECK: st2w { z0.s, z1.s }, p0, [x0, #6, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 6
|
||||
call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0,
|
||||
<vscale x 4 x float> %v1,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x float>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST2D
|
||||
;
|
||||
|
||||
define void @st2d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
|
||||
; CHECK-LABEL: st2d_i64:
|
||||
; CHECK: st2d { z0.d, z1.d }, p0, [x0, #8, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 8
|
||||
call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0,
|
||||
<vscale x 2 x i64> %v1,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x i64>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
|
||||
; CHECK-LABEL: st2d_f64:
|
||||
; CHECK: st2d { z0.d, z1.d }, p0, [x0, #10, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 10
|
||||
call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0,
|
||||
<vscale x 2 x double> %v1,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x double>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST3B
|
||||
;
|
||||
|
||||
define void @st3b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st3b_i8_valid_imm:
|
||||
; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, #3, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 3
|
||||
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3b_i8_invalid_imm_not_multiple_of_3_01(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st3b_i8_invalid_imm_not_multiple_of_3_01:
|
||||
; CHECK: rdvl x[[N:[0-9]+]], #4
|
||||
; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4
|
||||
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3b_i8_invalid_imm_not_multiple_of_3_02(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st3b_i8_invalid_imm_not_multiple_of_3_02:
|
||||
; CHECK: rdvl x[[N:[0-9]+]], #5
|
||||
; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5
|
||||
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st3b_i8_invalid_imm_out_of_lower_bound:
|
||||
; CHECK: rdvl x[[N:[0-9]+]], #-27
|
||||
; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -27
|
||||
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st3b_i8_invalid_imm_out_of_upper_bound:
|
||||
; CHECK: rdvl x[[N:[0-9]+]], #24
|
||||
; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 24
|
||||
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st3b_i8_valid_imm_lower_bound:
|
||||
; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, #-24, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -24
|
||||
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st3b_i8_valid_imm_upper_bound:
|
||||
; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, #21, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 21
|
||||
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST3H
|
||||
;
|
||||
|
||||
define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
|
||||
; CHECK-LABEL: st3h_i16:
|
||||
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, #6, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 6
|
||||
call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
|
||||
<vscale x 8 x i16> %v1,
|
||||
<vscale x 8 x i16> %v2,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x i16>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
|
||||
; CHECK-LABEL: st3h_f16:
|
||||
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, #9, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 9
|
||||
call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
|
||||
<vscale x 8 x half> %v1,
|
||||
<vscale x 8 x half> %v2,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x half>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST3W
|
||||
;
|
||||
|
||||
define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
|
||||
; CHECK-LABEL: st3w_i32:
|
||||
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, #12, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 12
|
||||
call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
|
||||
<vscale x 4 x i32> %v1,
|
||||
<vscale x 4 x i32> %v2,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x i32>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
|
||||
; CHECK-LABEL: st3w_f32:
|
||||
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, #15, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 15
|
||||
call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
|
||||
<vscale x 4 x float> %v1,
|
||||
<vscale x 4 x float> %v2,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x float>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST3D
|
||||
;
|
||||
|
||||
define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
|
||||
; CHECK-LABEL: st3d_i64:
|
||||
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, #18, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 18
|
||||
call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
|
||||
<vscale x 2 x i64> %v1,
|
||||
<vscale x 2 x i64> %v2,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x i64>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
|
||||
; CHECK-LABEL: st3d_f64:
|
||||
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, #-3, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 -3
|
||||
call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
|
||||
<vscale x 2 x double> %v1,
|
||||
<vscale x 2 x double> %v2,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x double>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4B
|
||||
;
|
||||
|
||||
define void @st4b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st4b_i8_valid_imm:
|
||||
; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #4, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4b_i8_invalid_imm_not_multiple_of_4_01(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_01:
|
||||
; CHECK: rdvl x[[N:[0-9]+]], #5
|
||||
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[N]]]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4b_i8_invalid_imm_not_multiple_of_4_02(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_02:
|
||||
; CHECK: rdvl x[[N:[0-9]+]], #6
|
||||
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[N]]]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 6
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4b_i8_invalid_imm_not_multiple_of_4_03(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_03:
|
||||
; CHECK: rdvl x[[N:[0-9]+]], #7
|
||||
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[N]]]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 7
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st4b_i8_invalid_imm_out_of_lower_bound:
|
||||
; FIXME: optimize OFFSET computation so that xOFFSET = (mul (RDVL #4) #9)
|
||||
; xM = -9 * 2^6
|
||||
; xP = RDVL * 2^-4
|
||||
; xBASE = RDVL * 2^-4 * -9 * 2^6 = RDVL * -36
|
||||
; CHECK: rdvl x[[N:[0-9]+]], #1
|
||||
; CHECK-DAG: mov x[[M:[0-9]+]], #-576
|
||||
; CHECK-DAG: lsr x[[P:[0-9]+]], x[[N]], #4
|
||||
; CHECK-DAG: mul x[[OFFSET:[0-9]+]], x[[P]], x[[M]]
|
||||
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[OFFSET]]]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -36
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st4b_i8_invalid_imm_out_of_upper_bound:
|
||||
; FIXME: optimize OFFSET computation so that xOFFSET = (shl (RDVL #16) #1)
|
||||
; xM = 2^9
|
||||
; xP = RDVL * 2^-4
|
||||
; xOFFSET = RDVL * 2^-4 * 2^9 = RDVL * 32
|
||||
; CHECK: rdvl x[[N:[0-9]+]], #1
|
||||
; CHECK-DAG: mov w[[M:[0-9]+]], #512
|
||||
; CHECK-DAG: lsr x[[P:[0-9]+]], x[[N]], #4
|
||||
; CHECK-DAG: mul x[[OFFSET:[0-9]+]], x[[P]], x[[M]]
|
||||
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[OFFSET]]]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 32
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st4b_i8_valid_imm_lower_bound:
|
||||
; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #-32, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -32
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
|
||||
; CHECK-LABEL: st4b_i8_valid_imm_upper_bound:
|
||||
; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #28, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 28
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4H
|
||||
;
|
||||
|
||||
define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
|
||||
; CHECK-LABEL: st4h_i16:
|
||||
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, #8, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 8
|
||||
call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0,
|
||||
<vscale x 8 x i16> %v1,
|
||||
<vscale x 8 x i16> %v2,
|
||||
<vscale x 8 x i16> %v3,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x i16>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
|
||||
; CHECK-LABEL: st4h_f16:
|
||||
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, #12, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 12
|
||||
call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0,
|
||||
<vscale x 8 x half> %v1,
|
||||
<vscale x 8 x half> %v2,
|
||||
<vscale x 8 x half> %v3,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x half>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4W
|
||||
;
|
||||
|
||||
define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
|
||||
; CHECK-LABEL: st4w_i32:
|
||||
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, #16, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 16
|
||||
call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0,
|
||||
<vscale x 4 x i32> %v1,
|
||||
<vscale x 4 x i32> %v2,
|
||||
<vscale x 4 x i32> %v3,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x i32>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
|
||||
; CHECK-LABEL: st4w_f32:
|
||||
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, #20, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 20
|
||||
call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0,
|
||||
<vscale x 4 x float> %v1,
|
||||
<vscale x 4 x float> %v2,
|
||||
<vscale x 4 x float> %v3,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x float>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4D
|
||||
;
|
||||
|
||||
define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
|
||||
; CHECK-LABEL: st4d_i64:
|
||||
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, #24, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 24
|
||||
call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0,
|
||||
<vscale x 2 x i64> %v1,
|
||||
<vscale x 2 x i64> %v2,
|
||||
<vscale x 2 x i64> %v3,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x i64>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
|
||||
; CHECK-LABEL: st4d_f64:
|
||||
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, #28, mul vl]
|
||||
; CHECK-NEXT: ret
|
||||
%base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 28
|
||||
call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0,
|
||||
<vscale x 2 x double> %v1,
|
||||
<vscale x 2 x double> %v2,
|
||||
<vscale x 2 x double> %v3,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x double>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
|
||||
|
||||
declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
|
||||
|
||||
declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
|
||||
|
|
@ -1,367 +0,0 @@
|
|||
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
|
||||
|
||||
;
|
||||
; ST2B
|
||||
;
|
||||
|
||||
define void @st2b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st2b_i8:
|
||||
; CHECK: st2b { z0.b, z1.b }, p0, [x0, x1]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i8, i8* %addr, i64 %offset
|
||||
%base = bitcast i8* %1 to <vscale x 16 x i8>*
|
||||
call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST2H
|
||||
;
|
||||
|
||||
define void @st2h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st2h_i16:
|
||||
; CHECK: st2h { z0.h, z1.h }, p0, [x0, x1, lsl #1]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i16, i16* %addr, i64 %offset
|
||||
%base = bitcast i16* %1 to <vscale x 8 x i16>*
|
||||
call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0,
|
||||
<vscale x 8 x i16> %v1,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x i16>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st2h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st2h_f16:
|
||||
; CHECK: st2h { z0.h, z1.h }, p0, [x0, x1, lsl #1]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr half, half* %addr, i64 %offset
|
||||
%base = bitcast half* %1 to <vscale x 8 x half>*
|
||||
call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0,
|
||||
<vscale x 8 x half> %v1,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x half>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST2W
|
||||
;
|
||||
|
||||
define void @st2w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st2w_i32:
|
||||
; CHECK: st2w { z0.s, z1.s }, p0, [x0, x1, lsl #2]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i32, i32* %addr, i64 %offset
|
||||
%base = bitcast i32* %1 to <vscale x 4 x i32>*
|
||||
call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0,
|
||||
<vscale x 4 x i32> %v1,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x i32>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st2w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st2w_f32:
|
||||
; CHECK: st2w { z0.s, z1.s }, p0, [x0, x1, lsl #2]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr float, float* %addr, i64 %offset
|
||||
%base = bitcast float* %1 to <vscale x 4 x float>*
|
||||
call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0,
|
||||
<vscale x 4 x float> %v1,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x float>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST2D
|
||||
;
|
||||
|
||||
define void @st2d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st2d_i64:
|
||||
; CHECK: st2d { z0.d, z1.d }, p0, [x0, x1, lsl #3]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i64, i64* %addr, i64 %offset
|
||||
%base = bitcast i64* %1 to <vscale x 2 x i64>*
|
||||
call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0,
|
||||
<vscale x 2 x i64> %v1,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x i64>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st2d_f64:
|
||||
; CHECK: st2d { z0.d, z1.d }, p0, [x0, x1, lsl #3]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr double, double* %addr, i64 %offset
|
||||
%base = bitcast double* %1 to <vscale x 2 x double>*
|
||||
call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0,
|
||||
<vscale x 2 x double> %v1,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x double>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST3B
|
||||
;
|
||||
|
||||
define void @st3b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st3b_i8:
|
||||
; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, x1]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i8, i8* %addr, i64 %offset
|
||||
%base = bitcast i8* %1 to <vscale x 16 x i8>*
|
||||
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST3H
|
||||
;
|
||||
|
||||
define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st3h_i16:
|
||||
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, x1, lsl #1]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i16, i16* %addr, i64 %offset
|
||||
%base = bitcast i16* %1 to <vscale x 8 x i16>*
|
||||
call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
|
||||
<vscale x 8 x i16> %v1,
|
||||
<vscale x 8 x i16> %v2,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x i16>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st3h_f16:
|
||||
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, x1, lsl #1]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr half, half* %addr, i64 %offset
|
||||
%base = bitcast half* %1 to <vscale x 8 x half>*
|
||||
call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
|
||||
<vscale x 8 x half> %v1,
|
||||
<vscale x 8 x half> %v2,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x half>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST3W
|
||||
;
|
||||
|
||||
define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st3w_i32:
|
||||
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, x1, lsl #2]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i32, i32* %addr, i64 %offset
|
||||
%base = bitcast i32* %1 to <vscale x 4 x i32>*
|
||||
call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
|
||||
<vscale x 4 x i32> %v1,
|
||||
<vscale x 4 x i32> %v2,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x i32>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st3w_f32:
|
||||
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, x1, lsl #2]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr float, float* %addr, i64 %offset
|
||||
%base = bitcast float* %1 to <vscale x 4 x float>*
|
||||
call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
|
||||
<vscale x 4 x float> %v1,
|
||||
<vscale x 4 x float> %v2,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x float>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST3D
|
||||
;
|
||||
|
||||
define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st3d_i64:
|
||||
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, x1, lsl #3]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i64, i64* %addr, i64 %offset
|
||||
%base = bitcast i64* %1 to <vscale x 2 x i64>*
|
||||
call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
|
||||
<vscale x 2 x i64> %v1,
|
||||
<vscale x 2 x i64> %v2,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x i64>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st3d_f64:
|
||||
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, x1, lsl #3]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr double, double* %addr, i64 %offset
|
||||
%base = bitcast double* %1 to <vscale x 2 x double>*
|
||||
call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
|
||||
<vscale x 2 x double> %v1,
|
||||
<vscale x 2 x double> %v2,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x double>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4B
|
||||
;
|
||||
|
||||
define void @st4b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st4b_i8:
|
||||
; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x1]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i8, i8* %addr, i64 %offset
|
||||
%base = bitcast i8* %1 to <vscale x 16 x i8>*
|
||||
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
|
||||
<vscale x 16 x i8> %v1,
|
||||
<vscale x 16 x i8> %v2,
|
||||
<vscale x 16 x i8> %v3,
|
||||
<vscale x 16 x i1> %pred,
|
||||
<vscale x 16 x i8>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4H
|
||||
;
|
||||
|
||||
define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st4h_i16:
|
||||
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x1, lsl #1]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i16, i16* %addr, i64 %offset
|
||||
%base = bitcast i16* %1 to <vscale x 8 x i16>*
|
||||
call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0,
|
||||
<vscale x 8 x i16> %v1,
|
||||
<vscale x 8 x i16> %v2,
|
||||
<vscale x 8 x i16> %v3,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x i16>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st4h_f16:
|
||||
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x1, lsl #1]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr half, half* %addr, i64 %offset
|
||||
%base = bitcast half* %1 to <vscale x 8 x half>*
|
||||
call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0,
|
||||
<vscale x 8 x half> %v1,
|
||||
<vscale x 8 x half> %v2,
|
||||
<vscale x 8 x half> %v3,
|
||||
<vscale x 8 x i1> %pred,
|
||||
<vscale x 8 x half>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4W
|
||||
;
|
||||
|
||||
define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st4w_i32:
|
||||
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x1, lsl #2]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i32, i32* %addr, i64 %offset
|
||||
%base = bitcast i32* %1 to <vscale x 4 x i32>*
|
||||
call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0,
|
||||
<vscale x 4 x i32> %v1,
|
||||
<vscale x 4 x i32> %v2,
|
||||
<vscale x 4 x i32> %v3,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x i32>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st4w_f32:
|
||||
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x1, lsl #2]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr float, float* %addr, i64 %offset
|
||||
%base = bitcast float* %1 to <vscale x 4 x float>*
|
||||
call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0,
|
||||
<vscale x 4 x float> %v1,
|
||||
<vscale x 4 x float> %v2,
|
||||
<vscale x 4 x float> %v3,
|
||||
<vscale x 4 x i1> %pred,
|
||||
<vscale x 4 x float>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
;
|
||||
; ST4D
|
||||
;
|
||||
|
||||
define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st4d_i64:
|
||||
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x1, lsl #3]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr i64, i64* %addr, i64 %offset
|
||||
%base = bitcast i64* %1 to <vscale x 2 x i64>*
|
||||
call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0,
|
||||
<vscale x 2 x i64> %v1,
|
||||
<vscale x 2 x i64> %v2,
|
||||
<vscale x 2 x i64> %v3,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x i64>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) {
|
||||
; CHECK-LABEL: st4d_f64:
|
||||
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x1, lsl #3]
|
||||
; CHECK-NEXT: ret
|
||||
%1 = getelementptr double, double* %addr, i64 %offset
|
||||
%base = bitcast double* %1 to <vscale x 2 x double>*
|
||||
call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0,
|
||||
<vscale x 2 x double> %v1,
|
||||
<vscale x 2 x double> %v2,
|
||||
<vscale x 2 x double> %v3,
|
||||
<vscale x 2 x i1> %pred,
|
||||
<vscale x 2 x double>* %base)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
|
||||
declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
|
||||
|
||||
declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
|
||||
declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
|
||||
|
||||
declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*)
|
||||
declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*)
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declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*)
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declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*)
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Reference in New Issue