forked from OSchip/llvm-project
Add an APInt version of SimplifyDemandedBits.
Patch by Zhou Sheng. llvm-svn: 35064
This commit is contained in:
Reid Spencer
parent
d9281784be
commit
1791f23803
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@ -319,10 +319,14 @@ namespace {
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/// most-complex to least-complex order.
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bool SimplifyCompare(CmpInst &I);
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bool SimplifyDemandedBits(Value *V, uint64_t Mask,
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bool SimplifyDemandedBits(Value *V, uint64_t DemandedMask,
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uint64_t &KnownZero, uint64_t &KnownOne,
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unsigned Depth = 0);
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bool SimplifyDemandedBits(Value *V, APInt DemandedMask,
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APInt& KnownZero, APInt& KnownOne,
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unsigned Depth = 0);
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Value *SimplifyDemandedVectorElts(Value *V, uint64_t DemandedElts,
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uint64_t &UndefElts, unsigned Depth = 0);
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@ -1545,6 +1549,525 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, uint64_t DemandedMask,
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return false;
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}
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/// SimplifyDemandedBits - This function attempts to replace V with a simpler
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/// value based on the demanded bits. When this function is called, it is known
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/// that only the bits set in DemandedMask of the result of V are ever used
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/// downstream. Consequently, depending on the mask and V, it may be possible
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/// to replace V with a constant or one of its operands. In such cases, this
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/// function does the replacement and returns true. In all other cases, it
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/// returns false after analyzing the expression and setting KnownOne and known
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/// to be one in the expression. KnownZero contains all the bits that are known
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/// to be zero in the expression. These are provided to potentially allow the
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/// caller (which might recursively be SimplifyDemandedBits itself) to simplify
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/// the expression. KnownOne and KnownZero always follow the invariant that
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/// KnownOne & KnownZero == 0. That is, a bit can't be both 1 and 0. Note that
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/// the bits in KnownOne and KnownZero may only be accurate for those bits set
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/// in DemandedMask. Note also that the bitwidth of V, DemandedMask, KnownZero
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/// and KnownOne must all be the same.
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bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask,
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APInt& KnownZero, APInt& KnownOne,
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unsigned Depth) {
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assert(V != 0 && "Null pointer of Value???");
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assert(Depth <= 6 && "Limit Search Depth");
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uint32_t BitWidth = DemandedMask.getBitWidth();
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const IntegerType *VTy = cast<IntegerType>(V->getType());
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assert(VTy->getBitWidth() == BitWidth &&
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KnownZero.getBitWidth() == BitWidth &&
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KnownOne.getBitWidth() == BitWidth &&
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"Value *V, DemandedMask, KnownZero and KnownOne \
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must have same BitWidth");
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if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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// We know all of the bits for a constant!
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KnownOne = CI->getValue() & DemandedMask;
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KnownZero = ~KnownOne & DemandedMask;
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return false;
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}
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//KnownZero.clear();
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//KnownOne.clear();
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if (!V->hasOneUse()) { // Other users may use these bits.
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if (Depth != 0) { // Not at the root.
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// Just compute the KnownZero/KnownOne bits to simplify things downstream.
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ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth);
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return false;
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}
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// If this is the root being simplified, allow it to have multiple uses,
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// just set the DemandedMask to all bits.
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DemandedMask = APInt::getAllOnesValue(BitWidth);
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} else if (DemandedMask == 0) { // Not demanding any bits from V.
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if (V != UndefValue::get(VTy))
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return UpdateValueUsesWith(V, UndefValue::get(VTy));
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return false;
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} else if (Depth == 6) { // Limit search depth.
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return false;
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}
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Instruction *I = dyn_cast<Instruction>(V);
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if (!I) return false; // Only analyze instructions.
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DemandedMask &= APInt::getAllOnesValue(BitWidth);
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APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
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APInt &RHSKnownZero = KnownZero, &RHSKnownOne = KnownOne;
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switch (I->getOpcode()) {
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default: break;
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case Instruction::And:
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// If either the LHS or the RHS are Zero, the result is zero.
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if (SimplifyDemandedBits(I->getOperand(1), DemandedMask,
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RHSKnownZero, RHSKnownOne, Depth+1))
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return true;
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assert((RHSKnownZero & RHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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// If something is known zero on the RHS, the bits aren't demanded on the
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// LHS.
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if (SimplifyDemandedBits(I->getOperand(0), DemandedMask & ~RHSKnownZero,
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LHSKnownZero, LHSKnownOne, Depth+1))
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return true;
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assert((LHSKnownZero & LHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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// If all of the demanded bits are known 1 on one side, return the other.
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// These bits cannot contribute to the result of the 'and'.
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if ((DemandedMask & ~LHSKnownZero & RHSKnownOne) ==
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(DemandedMask & ~LHSKnownZero))
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return UpdateValueUsesWith(I, I->getOperand(0));
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if ((DemandedMask & ~RHSKnownZero & LHSKnownOne) ==
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(DemandedMask & ~RHSKnownZero))
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return UpdateValueUsesWith(I, I->getOperand(1));
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// If all of the demanded bits in the inputs are known zeros, return zero.
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if ((DemandedMask & (RHSKnownZero|LHSKnownZero)) == DemandedMask)
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return UpdateValueUsesWith(I, Constant::getNullValue(VTy));
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// If the RHS is a constant, see if we can simplify it.
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if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnownZero))
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return UpdateValueUsesWith(I, I);
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// Output known-1 bits are only known if set in both the LHS & RHS.
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RHSKnownOne &= LHSKnownOne;
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// Output known-0 are known to be clear if zero in either the LHS | RHS.
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RHSKnownZero |= LHSKnownZero;
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break;
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case Instruction::Or:
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// If either the LHS or the RHS are One, the result is One.
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if (SimplifyDemandedBits(I->getOperand(1), DemandedMask,
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RHSKnownZero, RHSKnownOne, Depth+1))
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return true;
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assert((RHSKnownZero & RHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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// If something is known one on the RHS, the bits aren't demanded on the
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// LHS.
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if (SimplifyDemandedBits(I->getOperand(0), DemandedMask & ~RHSKnownOne,
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LHSKnownZero, LHSKnownOne, Depth+1))
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return true;
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assert((LHSKnownZero & LHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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// If all of the demanded bits are known zero on one side, return the other.
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// These bits cannot contribute to the result of the 'or'.
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if ((DemandedMask & ~LHSKnownOne & RHSKnownZero) ==
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(DemandedMask & ~LHSKnownOne))
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return UpdateValueUsesWith(I, I->getOperand(0));
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if ((DemandedMask & ~RHSKnownOne & LHSKnownZero) ==
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(DemandedMask & ~RHSKnownOne))
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return UpdateValueUsesWith(I, I->getOperand(1));
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// If all of the potentially set bits on one side are known to be set on
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// the other side, just use the 'other' side.
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if ((DemandedMask & (~RHSKnownZero) & LHSKnownOne) ==
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(DemandedMask & (~RHSKnownZero)))
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return UpdateValueUsesWith(I, I->getOperand(0));
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if ((DemandedMask & (~LHSKnownZero) & RHSKnownOne) ==
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(DemandedMask & (~LHSKnownZero)))
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return UpdateValueUsesWith(I, I->getOperand(1));
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// If the RHS is a constant, see if we can simplify it.
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if (ShrinkDemandedConstant(I, 1, DemandedMask))
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return UpdateValueUsesWith(I, I);
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// Output known-0 bits are only known if clear in both the LHS & RHS.
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RHSKnownZero &= LHSKnownZero;
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// Output known-1 are known to be set if set in either the LHS | RHS.
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RHSKnownOne |= LHSKnownOne;
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break;
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case Instruction::Xor: {
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if (SimplifyDemandedBits(I->getOperand(1), DemandedMask,
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RHSKnownZero, RHSKnownOne, Depth+1))
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return true;
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assert((RHSKnownZero & RHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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if (SimplifyDemandedBits(I->getOperand(0), DemandedMask,
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LHSKnownZero, LHSKnownOne, Depth+1))
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return true;
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assert((LHSKnownZero & LHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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// If all of the demanded bits are known zero on one side, return the other.
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// These bits cannot contribute to the result of the 'xor'.
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if ((DemandedMask & RHSKnownZero) == DemandedMask)
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return UpdateValueUsesWith(I, I->getOperand(0));
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if ((DemandedMask & LHSKnownZero) == DemandedMask)
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return UpdateValueUsesWith(I, I->getOperand(1));
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// Output known-0 bits are known if clear or set in both the LHS & RHS.
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APInt KnownZeroOut = (RHSKnownZero & LHSKnownZero) |
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(RHSKnownOne & LHSKnownOne);
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// Output known-1 are known to be set if set in only one of the LHS, RHS.
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APInt KnownOneOut = (RHSKnownZero & LHSKnownOne) |
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(RHSKnownOne & LHSKnownZero);
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// If all of the demanded bits are known to be zero on one side or the
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// other, turn this into an *inclusive* or.
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// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
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if ((DemandedMask & ~RHSKnownZero & ~LHSKnownZero) == 0) {
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Instruction *Or =
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BinaryOperator::createOr(I->getOperand(0), I->getOperand(1),
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I->getName());
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InsertNewInstBefore(Or, *I);
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return UpdateValueUsesWith(I, Or);
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}
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// If all of the demanded bits on one side are known, and all of the set
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// bits on that side are also known to be set on the other side, turn this
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// into an AND, as we know the bits will be cleared.
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// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
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if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) {
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// all known
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if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) {
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Constant *AndC = ConstantInt::get(~RHSKnownOne & DemandedMask);
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Instruction *And =
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BinaryOperator::createAnd(I->getOperand(0), AndC, "tmp");
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InsertNewInstBefore(And, *I);
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return UpdateValueUsesWith(I, And);
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}
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}
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// If the RHS is a constant, see if we can simplify it.
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// FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
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if (ShrinkDemandedConstant(I, 1, DemandedMask))
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return UpdateValueUsesWith(I, I);
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RHSKnownZero = KnownZeroOut;
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RHSKnownOne = KnownOneOut;
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break;
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}
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case Instruction::Select:
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if (SimplifyDemandedBits(I->getOperand(2), DemandedMask,
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RHSKnownZero, RHSKnownOne, Depth+1))
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return true;
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if (SimplifyDemandedBits(I->getOperand(1), DemandedMask,
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LHSKnownZero, LHSKnownOne, Depth+1))
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return true;
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assert((RHSKnownZero & RHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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assert((LHSKnownZero & LHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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// If the operands are constants, see if we can simplify them.
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if (ShrinkDemandedConstant(I, 1, DemandedMask))
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return UpdateValueUsesWith(I, I);
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if (ShrinkDemandedConstant(I, 2, DemandedMask))
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return UpdateValueUsesWith(I, I);
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// Only known if known in both the LHS and RHS.
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RHSKnownOne &= LHSKnownOne;
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RHSKnownZero &= LHSKnownZero;
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break;
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case Instruction::Trunc: {
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uint32_t truncBf =
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cast<IntegerType>(I->getOperand(0)->getType())->getBitWidth();
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if (SimplifyDemandedBits(I->getOperand(0), DemandedMask.zext(truncBf),
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RHSKnownZero.zext(truncBf), RHSKnownOne.zext(truncBf), Depth+1))
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return true;
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DemandedMask.trunc(BitWidth);
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RHSKnownZero.trunc(BitWidth);
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RHSKnownOne.trunc(BitWidth);
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assert((RHSKnownZero & RHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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break;
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}
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case Instruction::BitCast:
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if (!I->getOperand(0)->getType()->isInteger())
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return false;
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if (SimplifyDemandedBits(I->getOperand(0), DemandedMask,
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RHSKnownZero, RHSKnownOne, Depth+1))
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return true;
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assert((RHSKnownZero & RHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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break;
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case Instruction::ZExt: {
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// Compute the bits in the result that are not present in the input.
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const IntegerType *SrcTy = cast<IntegerType>(I->getOperand(0)->getType());
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APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
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DemandedMask &= SrcTy->getMask().zext(BitWidth);
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uint32_t zextBf = SrcTy->getBitWidth();
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if (SimplifyDemandedBits(I->getOperand(0), DemandedMask.trunc(zextBf),
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RHSKnownZero.trunc(zextBf), RHSKnownOne.trunc(zextBf), Depth+1))
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return true;
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DemandedMask.zext(BitWidth);
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RHSKnownZero.zext(BitWidth);
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RHSKnownOne.zext(BitWidth);
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assert((RHSKnownZero & RHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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// The top bits are known to be zero.
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RHSKnownZero |= NewBits;
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break;
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}
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case Instruction::SExt: {
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// Compute the bits in the result that are not present in the input.
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const IntegerType *SrcTy = cast<IntegerType>(I->getOperand(0)->getType());
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APInt NewBits(APInt::getAllOnesValue(BitWidth).shl(SrcTy->getBitWidth()));
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// Get the sign bit for the source type
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APInt InSignBit(APInt::getSignBit(SrcTy->getPrimitiveSizeInBits()));
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InSignBit.zext(BitWidth);
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APInt InputDemandedBits = DemandedMask &
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SrcTy->getMask().zext(BitWidth);
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// If any of the sign extended bits are demanded, we know that the sign
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// bit is demanded.
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if ((NewBits & DemandedMask) != 0)
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InputDemandedBits |= InSignBit;
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uint32_t sextBf = SrcTy->getBitWidth();
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if (SimplifyDemandedBits(I->getOperand(0), InputDemandedBits.trunc(sextBf),
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RHSKnownZero.trunc(sextBf), RHSKnownOne.trunc(sextBf), Depth+1))
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return true;
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InputDemandedBits.zext(BitWidth);
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RHSKnownZero.zext(BitWidth);
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RHSKnownOne.zext(BitWidth);
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assert((RHSKnownZero & RHSKnownOne) == 0 &&
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"Bits known to be one AND zero?");
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// If the sign bit of the input is known set or clear, then we know the
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// top bits of the result.
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// If the input sign bit is known zero, or if the NewBits are not demanded
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// convert this into a zero extension.
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if ((RHSKnownZero & InSignBit) != 0 || (NewBits & ~DemandedMask) == NewBits)
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{
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// Convert to ZExt cast
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CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName(), I);
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return UpdateValueUsesWith(I, NewCast);
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} else if ((RHSKnownOne & InSignBit) != 0) { // Input sign bit known set
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RHSKnownOne |= NewBits;
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RHSKnownZero &= ~NewBits;
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} else { // Input sign bit unknown
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RHSKnownZero &= ~NewBits;
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RHSKnownOne &= ~NewBits;
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}
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break;
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}
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case Instruction::Add: {
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// Figure out what the input bits are. If the top bits of the and result
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// are not demanded, then the add doesn't demand them from its input
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// either.
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unsigned NLZ = DemandedMask.countLeadingZeros();
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// If there is a constant on the RHS, there are a variety of xformations
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// we can do.
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if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
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// If null, this should be simplified elsewhere. Some of the xforms here
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// won't work if the RHS is zero.
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if (RHS->isZero())
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break;
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// If the top bit of the output is demanded, demand everything from the
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// input. Otherwise, we demand all the input bits except NLZ top bits.
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APInt InDemandedBits(APInt::getAllOnesValue(BitWidth).lshr(NLZ));
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// Find information about known zero/one bits in the input.
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if (SimplifyDemandedBits(I->getOperand(0), InDemandedBits,
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LHSKnownZero, LHSKnownOne, Depth+1))
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return true;
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// If the RHS of the add has bits set that can't affect the input, reduce
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// the constant.
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if (ShrinkDemandedConstant(I, 1, InDemandedBits))
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return UpdateValueUsesWith(I, I);
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// Avoid excess work.
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if (LHSKnownZero == 0 && LHSKnownOne == 0)
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break;
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// Turn it into OR if input bits are zero.
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if ((LHSKnownZero & RHS->getValue()) == RHS->getValue()) {
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Instruction *Or =
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BinaryOperator::createOr(I->getOperand(0), I->getOperand(1),
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I->getName());
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InsertNewInstBefore(Or, *I);
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return UpdateValueUsesWith(I, Or);
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}
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// We can say something about the output known-zero and known-one bits,
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// depending on potential carries from the input constant and the
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// unknowns. For example if the LHS is known to have at most the 0x0F0F0
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// bits set and the RHS constant is 0x01001, then we know we have a known
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// one mask of 0x00001 and a known zero mask of 0xE0F0E.
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// To compute this, we first compute the potential carry bits. These are
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// the bits which may be modified. I'm not aware of a better way to do
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// this scan.
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APInt RHSVal(RHS->getValue());
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bool CarryIn = false;
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APInt CarryBits(BitWidth, 0);
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const uint64_t *LHSKnownZeroRawVal = LHSKnownZero.getRawData(),
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*RHSRawVal = RHSVal.getRawData();
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for (uint32_t i = 0; i != RHSVal.getNumWords(); ++i) {
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uint64_t AddVal = ~LHSKnownZeroRawVal[i] + RHSRawVal[i],
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XorVal = ~LHSKnownZeroRawVal[i] ^ RHSRawVal[i];
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uint64_t WordCarryBits = AddVal ^ XorVal + CarryIn;
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if (AddVal < RHSRawVal[i])
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CarryIn = true;
|
||||
else
|
||||
CarryIn = false;
|
||||
CarryBits.setWordToValue(i, WordCarryBits);
|
||||
}
|
||||
|
||||
// Now that we know which bits have carries, compute the known-1/0 sets.
|
||||
|
||||
// Bits are known one if they are known zero in one operand and one in the
|
||||
// other, and there is no input carry.
|
||||
RHSKnownOne = ((LHSKnownZero & RHSVal) |
|
||||
(LHSKnownOne & ~RHSVal)) & ~CarryBits;
|
||||
|
||||
// Bits are known zero if they are known zero in both operands and there
|
||||
// is no input carry.
|
||||
RHSKnownZero = LHSKnownZero & ~RHSVal & ~CarryBits;
|
||||
} else {
|
||||
// If the high-bits of this ADD are not demanded, then it does not demand
|
||||
// the high bits of its LHS or RHS.
|
||||
if ((DemandedMask & APInt::getSignBit(BitWidth)) == 0) {
|
||||
// Right fill the mask of bits for this ADD to demand the most
|
||||
// significant bit and all those below it.
|
||||
APInt DemandedFromOps = APInt::getAllOnesValue(BitWidth).lshr(NLZ);
|
||||
if (SimplifyDemandedBits(I->getOperand(0), DemandedFromOps,
|
||||
LHSKnownZero, LHSKnownOne, Depth+1))
|
||||
return true;
|
||||
if (SimplifyDemandedBits(I->getOperand(1), DemandedFromOps,
|
||||
LHSKnownZero, LHSKnownOne, Depth+1))
|
||||
return true;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
case Instruction::Sub:
|
||||
// If the high-bits of this SUB are not demanded, then it does not demand
|
||||
// the high bits of its LHS or RHS.
|
||||
if ((DemandedMask & APInt::getSignBit(BitWidth)) == 0) {
|
||||
// Right fill the mask of bits for this SUB to demand the most
|
||||
// significant bit and all those below it.
|
||||
unsigned NLZ = DemandedMask.countLeadingZeros();
|
||||
APInt DemandedFromOps(APInt::getAllOnesValue(BitWidth).lshr(NLZ));
|
||||
if (SimplifyDemandedBits(I->getOperand(0), DemandedFromOps,
|
||||
LHSKnownZero, LHSKnownOne, Depth+1))
|
||||
return true;
|
||||
if (SimplifyDemandedBits(I->getOperand(1), DemandedFromOps,
|
||||
LHSKnownZero, LHSKnownOne, Depth+1))
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
case Instruction::Shl:
|
||||
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
|
||||
uint64_t ShiftAmt = SA->getZExtValue();
|
||||
if (SimplifyDemandedBits(I->getOperand(0), DemandedMask.lshr(ShiftAmt),
|
||||
RHSKnownZero, RHSKnownOne, Depth+1))
|
||||
return true;
|
||||
assert((RHSKnownZero & RHSKnownOne) == 0 &&
|
||||
"Bits known to be one AND zero?");
|
||||
RHSKnownZero <<= ShiftAmt;
|
||||
RHSKnownOne <<= ShiftAmt;
|
||||
// low bits known zero.
|
||||
RHSKnownZero |= APInt::getAllOnesValue(ShiftAmt).zext(BitWidth);
|
||||
}
|
||||
break;
|
||||
case Instruction::LShr:
|
||||
// For a logical shift right
|
||||
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
|
||||
unsigned ShiftAmt = SA->getZExtValue();
|
||||
|
||||
APInt TypeMask(APInt::getAllOnesValue(BitWidth));
|
||||
// Unsigned shift right.
|
||||
if (SimplifyDemandedBits(I->getOperand(0),
|
||||
(DemandedMask.shl(ShiftAmt)) & TypeMask,
|
||||
RHSKnownZero, RHSKnownOne, Depth+1))
|
||||
return true;
|
||||
assert((RHSKnownZero & RHSKnownOne) == 0 &&
|
||||
"Bits known to be one AND zero?");
|
||||
// Compute the new bits that are at the top now.
|
||||
APInt HighBits(APInt::getAllOnesValue(ShiftAmt).zext(BitWidth).shl(
|
||||
BitWidth - ShiftAmt));
|
||||
RHSKnownZero &= TypeMask;
|
||||
RHSKnownOne &= TypeMask;
|
||||
RHSKnownZero = APIntOps::lshr(RHSKnownZero, ShiftAmt);
|
||||
RHSKnownOne = APIntOps::lshr(RHSKnownOne, ShiftAmt);
|
||||
RHSKnownZero |= HighBits; // high bits known zero.
|
||||
}
|
||||
break;
|
||||
case Instruction::AShr:
|
||||
// If this is an arithmetic shift right and only the low-bit is set, we can
|
||||
// always convert this into a logical shr, even if the shift amount is
|
||||
// variable. The low bit of the shift cannot be an input sign bit unless
|
||||
// the shift amount is >= the size of the datatype, which is undefined.
|
||||
if (DemandedMask == 1) {
|
||||
// Perform the logical shift right.
|
||||
Value *NewVal = BinaryOperator::createLShr(
|
||||
I->getOperand(0), I->getOperand(1), I->getName());
|
||||
InsertNewInstBefore(cast<Instruction>(NewVal), *I);
|
||||
return UpdateValueUsesWith(I, NewVal);
|
||||
}
|
||||
|
||||
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
|
||||
unsigned ShiftAmt = SA->getZExtValue();
|
||||
|
||||
APInt TypeMask(APInt::getAllOnesValue(BitWidth));
|
||||
// Signed shift right.
|
||||
if (SimplifyDemandedBits(I->getOperand(0),
|
||||
(DemandedMask.shl(ShiftAmt)) & TypeMask,
|
||||
RHSKnownZero, RHSKnownOne, Depth+1))
|
||||
return true;
|
||||
assert((RHSKnownZero & RHSKnownOne) == 0 &&
|
||||
"Bits known to be one AND zero?");
|
||||
// Compute the new bits that are at the top now.
|
||||
APInt HighBits(APInt::getAllOnesValue(ShiftAmt).zext(BitWidth).shl(
|
||||
BitWidth - ShiftAmt));
|
||||
RHSKnownZero &= TypeMask;
|
||||
RHSKnownOne &= TypeMask;
|
||||
RHSKnownZero = APIntOps::lshr(RHSKnownZero, ShiftAmt);
|
||||
RHSKnownOne = APIntOps::lshr(RHSKnownOne, ShiftAmt);
|
||||
|
||||
// Handle the sign bits.
|
||||
APInt SignBit(APInt::getSignBit(BitWidth));
|
||||
// Adjust to where it is now in the mask.
|
||||
SignBit = APIntOps::lshr(SignBit, ShiftAmt);
|
||||
|
||||
// If the input sign bit is known to be zero, or if none of the top bits
|
||||
// are demanded, turn this into an unsigned shift right.
|
||||
if ((RHSKnownZero & SignBit) != 0 ||
|
||||
(HighBits & ~DemandedMask) == HighBits) {
|
||||
// Perform the logical shift right.
|
||||
Value *NewVal = BinaryOperator::createLShr(
|
||||
I->getOperand(0), SA, I->getName());
|
||||
InsertNewInstBefore(cast<Instruction>(NewVal), *I);
|
||||
return UpdateValueUsesWith(I, NewVal);
|
||||
} else if ((RHSKnownOne & SignBit) != 0) { // New bits are known one.
|
||||
RHSKnownOne |= HighBits;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
// If the client is only demanding bits that we know, return the known
|
||||
// constant.
|
||||
if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask)
|
||||
return UpdateValueUsesWith(I, ConstantInt::get(RHSKnownOne));
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
/// SimplifyDemandedVectorElts - The specified value producecs a vector with
|
||||
/// 64 or fewer elements. DemandedElts contains the set of elements that are
|
||||
|
|
|
|||
Loading…
Reference in New Issue