forked from OSchip/llvm-project
parent
994f2d1406
commit
178f0f1405
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@ -4,7 +4,7 @@
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class Arg { int a; }
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class TheArg : Arg { let a = 1; }
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def TheArg : Arg { let a = 1; }
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class Super<Arg F> {
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