forked from OSchip/llvm-project
[AArch64] Add support for NEON scalar signed saturating accumulated of unsigned
value and unsigned saturating accumulate of signed value instructions. llvm-svn: 192800
This commit is contained in:
Chad Rosier
parent
5078ea2bd9
commit
178b1cefc7
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@ -191,4 +191,9 @@ def int_aarch64_neon_vchi : Neon_ICmp_Intrinsic;
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// Scalar Compare Bitwise Test Bits
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def int_aarch64_neon_vtstd : Neon_ICmp_Intrinsic;
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// Scalar Signed Saturating Accumulated of Unsigned Value
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def int_aarch64_neon_vuqadd : Neon_2Arg_Intrinsic;
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// Scalar Unsigned Saturating Accumulated of Unsigned Value
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def int_aarch64_neon_vsqadd : Neon_2Arg_Intrinsic;
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}
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@ -3116,7 +3116,7 @@ def ST1_4V_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
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// End of vector load/store multiple N-element structure(class SIMD lselem)
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// Scalar Arithmetic
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// Scalar Three Same
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class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
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: NeonI_Scalar3Same<u, 0b11, opcode,
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@ -3264,6 +3264,29 @@ multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>{
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[], NoItinerary>;
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}
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multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
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string asmop> {
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let Constraints = "$Src = $Rd" in {
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def bb : NeonI_Scalar2SameMisc<u, 0b00, opcode,
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(outs FPR8:$Rd), (ins FPR8:$Src, FPR8:$Rn),
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!strconcat(asmop, " $Rd, $Rn"),
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[], NoItinerary>;
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def hh : NeonI_Scalar2SameMisc<u, 0b01, opcode,
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(outs FPR16:$Rd), (ins FPR16:$Src, FPR16:$Rn),
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!strconcat(asmop, " $Rd, $Rn"),
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[], NoItinerary>;
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def ss : NeonI_Scalar2SameMisc<u, 0b10, opcode,
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(outs FPR32:$Rd), (ins FPR32:$Src, FPR32:$Rn),
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!strconcat(asmop, " $Rd, $Rn"),
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[], NoItinerary>;
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def dd: NeonI_Scalar2SameMisc<u, 0b11, opcode,
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(outs FPR64:$Rd), (ins FPR64:$Src, FPR64:$Rn),
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!strconcat(asmop, " $Rd, $Rn"),
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[], NoItinerary>;
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}
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}
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multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
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SDPatternOperator Dopnode,
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Instruction INSTS,
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@ -3283,7 +3306,6 @@ multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
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(INSTD FPR64:$Rn)>;
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}
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// AdvSIMD Scalar Two Registers Miscellaneous
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class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
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: NeonI_Scalar2SameMisc<u, 0b11, opcode,
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(outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
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@ -3311,6 +3333,22 @@ multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
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(INSTD FPR64:$Rn)>;
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}
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multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
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SDPatternOperator opnode,
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Instruction INSTB,
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Instruction INSTH,
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Instruction INSTS,
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Instruction INSTD> {
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def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
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(INSTB FPR8:$Src, FPR8:$Rn)>;
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def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
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(INSTH FPR16:$Src, FPR16:$Rn)>;
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def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
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(INSTS FPR32:$Src, FPR32:$Rn)>;
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def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
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(INSTD FPR64:$Src, FPR64:$Rn)>;
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}
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// Scalar Integer Add
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let isCommutable = 1 in {
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def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
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@ -3539,6 +3577,18 @@ defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
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defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
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SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
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// Scalar Signed Saturating Accumulated of Unsigned Value
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defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
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defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
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SUQADDbb, SUQADDhh,
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SUQADDss, SUQADDdd>;
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// Scalar Unsigned Saturating Accumulated of Unsigned Value
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defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
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defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
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USQADDbb, USQADDhh,
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USQADDss, USQADDdd>;
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// Scalar Reduce Pairwise
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multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
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@ -169,3 +169,107 @@ define <1 x i64> @test_sqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
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;CHECK: sqsub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
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ret <1 x i64> %tmp1
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}
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define i8 @test_vuqaddb_s8(i8 %a, i8 %b) {
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; CHECK: test_vuqaddb_s8
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; CHECK: suqadd {{b[0-9]+}}, {{b[0-9]+}}
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entry:
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%vuqadd.i = insertelement <1 x i8> undef, i8 %a, i32 0
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%vuqadd1.i = insertelement <1 x i8> undef, i8 %b, i32 0
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%vuqadd2.i = call <1 x i8> @llvm.aarch64.neon.vuqadd.v1i8(<1 x i8> %vuqadd.i, <1 x i8> %vuqadd1.i)
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%0 = extractelement <1 x i8> %vuqadd2.i, i32 0
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ret i8 %0
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}
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declare <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8>, <1 x i8>)
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define i16 @test_vuqaddh_s16(i16 %a, i16 %b) {
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; CHECK: test_vuqaddh_s16
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; CHECK: suqadd {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%vuqadd.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vuqadd1.i = insertelement <1 x i16> undef, i16 %b, i32 0
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%vuqadd2.i = call <1 x i16> @llvm.aarch64.neon.vuqadd.v1i16(<1 x i16> %vuqadd.i, <1 x i16> %vuqadd1.i)
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%0 = extractelement <1 x i16> %vuqadd2.i, i32 0
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ret i16 %0
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}
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declare <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16>, <1 x i16>)
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define i32 @test_vuqadds_s32(i32 %a, i32 %b) {
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; CHECK: test_vuqadds_s32
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; CHECK: suqadd {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vuqadd.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vuqadd1.i = insertelement <1 x i32> undef, i32 %b, i32 0
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%vuqadd2.i = call <1 x i32> @llvm.aarch64.neon.vuqadd.v1i32(<1 x i32> %vuqadd.i, <1 x i32> %vuqadd1.i)
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%0 = extractelement <1 x i32> %vuqadd2.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vsqadd.v1i32(<1 x i32>, <1 x i32>)
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define i64 @test_vuqaddd_s64(i64 %a, i64 %b) {
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; CHECK: test_vuqaddd_s64
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; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vuqadd.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vuqadd1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vuqadd2.i = call <1 x i64> @llvm.aarch64.neon.vuqadd.v1i64(<1 x i64> %vuqadd.i, <1 x i64> %vuqadd1.i)
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%0 = extractelement <1 x i64> %vuqadd2.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.vsqadd.v1i64(<1 x i64>, <1 x i64>)
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define i8 @test_vsqaddb_u8(i8 %a, i8 %b) {
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; CHECK: test_vsqaddb_u8
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; CHECK: usqadd {{b[0-9]+}}, {{b[0-9]+}}
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entry:
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%vsqadd.i = insertelement <1 x i8> undef, i8 %a, i32 0
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%vsqadd1.i = insertelement <1 x i8> undef, i8 %b, i32 0
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%vsqadd2.i = call <1 x i8> @llvm.aarch64.neon.vsqadd.v1i8(<1 x i8> %vsqadd.i, <1 x i8> %vsqadd1.i)
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%0 = extractelement <1 x i8> %vsqadd2.i, i32 0
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ret i8 %0
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}
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declare <1 x i8> @llvm.aarch64.neon.vuqadd.v1i8(<1 x i8>, <1 x i8>)
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define i16 @test_vsqaddh_u16(i16 %a, i16 %b) {
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; CHECK: test_vsqaddh_u16
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; CHECK: usqadd {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%vsqadd.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vsqadd1.i = insertelement <1 x i16> undef, i16 %b, i32 0
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%vsqadd2.i = call <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16> %vsqadd.i, <1 x i16> %vsqadd1.i)
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%0 = extractelement <1 x i16> %vsqadd2.i, i32 0
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ret i16 %0
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}
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declare <1 x i16> @llvm.aarch64.neon.vuqadd.v1i16(<1 x i16>, <1 x i16>)
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define i32 @test_vsqadds_u32(i32 %a, i32 %b) {
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; CHECK: test_vsqadds_u32
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; CHECK: usqadd {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vsqadd.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vsqadd1.i = insertelement <1 x i32> undef, i32 %b, i32 0
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%vsqadd2.i = call <1 x i32> @llvm.aarch64.neon.vsqadd.v1i32(<1 x i32> %vsqadd.i, <1 x i32> %vsqadd1.i)
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%0 = extractelement <1 x i32> %vsqadd2.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vuqadd.v1i32(<1 x i32>, <1 x i32>)
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define i64 @test_vsqaddd_u64(i64 %a, i64 %b) {
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; CHECK: test_vsqaddd_u64
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; CHECK: usqadd {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vsqadd.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vsqadd1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vsqadd2.i = call <1 x i64> @llvm.aarch64.neon.vsqadd.v1i64(<1 x i64> %vsqadd.i, <1 x i64> %vsqadd1.i)
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%0 = extractelement <1 x i64> %vsqadd2.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.vuqadd.v1i64(<1 x i64>, <1 x i64>)
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@ -4396,3 +4396,47 @@
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: cmtst b20, d21, d22
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Scalar Signed Saturating Accumulated of Unsigned Value
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//----------------------------------------------------------------------
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suqadd b0, h1
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suqadd h0, s1
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suqadd s0, d1
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suqadd d0, b0
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: suqadd b0, h1
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: suqadd h0, s1
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: suqadd s0, d1
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: suqadd d0, b0
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Scalar Unsigned Saturating Accumulated of Unsigned Value
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//----------------------------------------------------------------------
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usqadd b0, h1
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usqadd h0, s1
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usqadd s0, d1
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usqadd d0, b1
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: usqadd b0, h1
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: usqadd h0, s1
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: usqadd s0, d1
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: usqadd d0, b1
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// CHECK-ERROR: ^
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@ -52,3 +52,30 @@
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// CHECK: uqsub s20, s21, s2 // encoding: [0xb4,0x2e,0xa2,0x7e]
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// CHECK: uqsub d17, d31, d8 // encoding: [0xf1,0x2f,0xe8,0x7e]
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//----------------------------------------------------------------------
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// Signed Saturating Accumulated of Unsigned Value
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//----------------------------------------------------------------------
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suqadd b19, b14
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suqadd h20, h15
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suqadd s21, s12
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suqadd d18, d22
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// CHECK: suqadd b19, b14 // encoding: [0xd3,0x39,0x20,0x5e]
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// CHECK: suqadd h20, h15 // encoding: [0xf4,0x39,0x60,0x5e]
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// CHECK: suqadd s21, s12 // encoding: [0x95,0x39,0xa0,0x5e]
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// CHECK: suqadd d18, d22 // encoding: [0xd2,0x3a,0xe0,0x5e]
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//----------------------------------------------------------------------
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// Unsigned Saturating Accumulated of Unsigned Value
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//----------------------------------------------------------------------
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usqadd b19, b14
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usqadd h20, h15
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usqadd s21, s12
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usqadd d18, d22
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// CHECK: usqadd b19, b14 // encoding: [0xd3,0x39,0x20,0x7e]
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// CHECK: usqadd h20, h15 // encoding: [0xf4,0x39,0x60,0x7e]
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// CHECK: usqadd s21, s12 // encoding: [0x95,0x39,0xa0,0x7e]
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// CHECK: usqadd d18, d22 // encoding: [0xd2,0x3a,0xe0,0x7e]
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@ -1623,3 +1623,27 @@
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0xf5,0x79,0x60,0x7e
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0x94,0x79,0xa0,0x7e
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0x92,0x79,0xe0,0x7e
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#----------------------------------------------------------------------
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# Signed Saturating Accumulated of Unsigned Value
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#----------------------------------------------------------------------
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# CHECK: suqadd b19, b14
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# CHECK: suqadd h20, h15
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# CHECK: suqadd s21, s12
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# CHECK: suqadd d18, d22
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0xd3,0x39,0x20,0x5e
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0xf4,0x39,0x60,0x5e
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0x95,0x39,0xa0,0x5e
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0xd2,0x3a,0xe0,0x5e
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#----------------------------------------------------------------------
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# Unsigned Saturating Accumulated of Unsigned Value
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#----------------------------------------------------------------------
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# CHECK: usqadd b19, b14
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# CHECK: usqadd h20, h15
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# CHECK: usqadd s21, s12
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# CHECK: usqadd d18, d22
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0xd3,0x39,0x20,0x7e
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0xf4,0x39,0x60,0x7e
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0x95,0x39,0xa0,0x7e
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0xd2,0x3a,0xe0,0x7e
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