forked from OSchip/llvm-project
[AMDGPU][GFX90a][DOC][NFC] Update assembler syntax description
Summary of changes: - Update MUBUF lds syntax (see https://reviews.llvm.org/D124485). - Update SMEM syntax (see https://reviews.llvm.org/D127314). - Enable src0=literal for v_madak*, v_madmk* (see https://reviews.llvm.org/D111067). - Correct src0 operands of v_accvgpr_write_b32. - Correct description of s_getreg/s_setreg (add TBA/TMA). - Remove SYSMSG_OP_HOST_TRAP_ACK message. - Minor bug fixing and improvements.
This commit is contained in:
Dmitry Preobrazhensky
parent
675080a453
commit
1774f2e326
File diff suppressed because it is too large
Load Diff
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@ -41,18 +41,22 @@ or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
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Defined register *names* include:
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=================== ==========================================
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Name Description
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=================== ==========================================
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HW_REG_MODE Shader writeable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID Id of wave, simd, compute unit, etc.
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HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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HW_REG_LDS_ALLOC Per-wave LDS allocation.
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HW_REG_IB_STS Counters of outstanding instructions.
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HW_REG_SH_MEM_BASES Memory aperture.
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=================== ==========================================
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============================== ==========================================
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Name Description
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============================== ==========================================
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HW_REG_MODE Shader writeable mode bits.
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HW_REG_STATUS Shader read-only status.
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HW_REG_TRAPSTS Trap status.
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HW_REG_HW_ID Id of wave, simd, compute unit, etc.
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HW_REG_GPR_ALLOC Per-wave SGPR and VGPR allocation.
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HW_REG_LDS_ALLOC Per-wave LDS allocation.
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HW_REG_IB_STS Counters of outstanding instructions.
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HW_REG_SH_MEM_BASES Memory aperture.
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HW_REG_TBA_LO tba_lo register.
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HW_REG_TBA_HI tba_hi register.
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HW_REG_TMA_LO tma_lo register.
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HW_REG_TMA_HI tma_hi register.
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============================== ==========================================
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Examples:
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@ -1,13 +0,0 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_imm16_2:
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imm16
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=====
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A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_imm16:
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.. _amdgpu_synid_gfx90a_imm16_73139a:
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imm16
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_imm16_1:
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.. _amdgpu_synid_gfx90a_imm16_a04fb3:
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imm16
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_m:
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.. _amdgpu_synid_gfx90a_m_254bcb:
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m
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=
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_m_1:
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.. _amdgpu_synid_gfx90a_m_f5d306:
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m
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=
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@ -67,7 +67,6 @@ Each message type supports specific operations:
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MSG_GET_DOORBELL 10 \- \- \-
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MSG_SYSMSG 15 SYSMSG_OP_ECC_ERR_INTERRUPT 1 \-
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\ SYSMSG_OP_REG_RD 2 \-
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\ SYSMSG_OP_HOST_TRAP_ACK 3 \-
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\ SYSMSG_OP_TTRACE_PC 4 \-
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====================== ========== ============================== ============ ==========
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@ -0,0 +1,13 @@
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_opt_0d447d:
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opt
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===
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This is an optional operand. It must be used if and only if :ref:`lds<amdgpu_synid_lds>` is omitted.
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_opt:
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.. _amdgpu_synid_gfx90a_opt_847aed:
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opt
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===
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_saddr_1:
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.. _amdgpu_synid_gfx90a_saddr_6060e5:
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saddr
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=====
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An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
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Either this operand or :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_3>` must be set to :ref:`off<amdgpu_synid_off>`.
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Either this operand or :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_76b997>` must be set to :ref:`off<amdgpu_synid_off>`.
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*Size:* 1 dword.
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@ -5,14 +5,14 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_saddr:
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.. _amdgpu_synid_gfx90a_saddr_a37373:
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saddr
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=====
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An optional 64-bit flat global address. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
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See :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` for description of available addressing modes.
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See :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` for description of available addressing modes.
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*Size:* 2 dwords.
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sbase_1:
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.. _amdgpu_synid_gfx90a_sbase_010ce0:
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sbase
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sbase:
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.. _amdgpu_synid_gfx90a_sbase_044055:
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sbase
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sbase_2:
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.. _amdgpu_synid_gfx90a_sbase_0cd545:
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sbase
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=====
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@ -5,7 +5,7 @@
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdata_3:
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.. _amdgpu_synid_gfx90a_sdata_595c25:
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sdata
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=====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdata_5:
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.. _amdgpu_synid_gfx90a_sdata_7cbd60:
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sdata
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=====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdata:
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.. _amdgpu_synid_gfx90a_sdata_aefe00:
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sdata
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=====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdata_2:
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.. _amdgpu_synid_gfx90a_sdata_c6aec1:
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sdata
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=====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdata_4:
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.. _amdgpu_synid_gfx90a_sdata_e9f591:
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sdata
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=====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdata_1:
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.. _amdgpu_synid_gfx90a_sdata_eb6f2a:
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sdata
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=====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdst_5:
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.. _amdgpu_synid_gfx90a_sdst_06b266:
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sdst
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====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdst_3:
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.. _amdgpu_synid_gfx90a_sdst_0804b1:
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sdst
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====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdst_4:
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.. _amdgpu_synid_gfx90a_sdst_362c37:
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sdst
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====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdst_1:
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.. _amdgpu_synid_gfx90a_sdst_3bc700:
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sdst
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====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdst_7:
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.. _amdgpu_synid_gfx90a_sdst_59204c:
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sdst
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====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdst_2:
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.. _amdgpu_synid_gfx90a_sdst_718cc4:
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sdst
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====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdst:
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.. _amdgpu_synid_gfx90a_sdst_94342d:
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sdst
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====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_sdst_6:
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.. _amdgpu_synid_gfx90a_sdst_a319e6:
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sdst
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====
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_simm32_2:
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.. _amdgpu_synid_gfx90a_simm32_6f0844:
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simm32
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======
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A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
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The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
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The value is converted to *f32* as described :ref:`here<amdgpu_synid_conv>`.
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_simm32:
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.. _amdgpu_synid_gfx90a_simm32_a3e80c:
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simm32
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======
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_simm32_1:
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.. _amdgpu_synid_gfx90a_simm32_be0c1c:
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simm32
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======
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A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
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The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
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The value is converted to *f16* as described :ref:`here<amdgpu_synid_conv>`.
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_soffset:
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.. _amdgpu_synid_gfx90a_soffset_4318ca:
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soffset
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=======
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_soffset_1:
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.. _amdgpu_synid_gfx90a_soffset_8a17c8:
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soffset
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=======
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An offset added to the base address to get memory address.
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An offset from the base address.
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* If offset is specified as a register, it supplies an unsigned byte offset.
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* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
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Note that an *immediate* offset may be specified using either :ref:`simm21<amdgpu_synid_simm21>` operand or :ref:`offset21s<amdgpu_synid_smem_offset21s>` modifier, but not both.
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*Size:* 1 dword.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack_mask<amdgpu_synid_xnack_mask>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`simm21<amdgpu_synid_simm21>`
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_soffset_2:
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.. _amdgpu_synid_gfx90a_soffset_ba92ce:
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soffset
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=======
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An unsigned 20-bit offset added to the base address to get memory address.
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An unsigned offset from the base address. My be specified as either a register or a 20-bit immediate.
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Note that an *immediate* offset may be specified using either :ref:`uimm20<amdgpu_synid_uimm20>` operand or :ref:`offset20u<amdgpu_synid_smem_offset20u>` modifier, but not both.
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*Size:* 1 dword.
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_src_3:
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.. _amdgpu_synid_gfx90a_src_4de5c6:
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src
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===
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_src_2:
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.. _amdgpu_synid_gfx90a_src_56ed80:
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src
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===
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_src_6:
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src
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===
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Instruction input.
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*Size:* 1 dword.
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*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`fconst<amdgpu_synid_fconst>`
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_src_11:
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.. _amdgpu_synid_gfx90a_src_64ea89:
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src
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===
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_src_9:
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.. _amdgpu_synid_gfx90a_src_6cfc4e:
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src
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===
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_src_8:
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.. _amdgpu_synid_gfx90a_src_a578ba:
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src
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===
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_src_7:
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.. _amdgpu_synid_gfx90a_src_af08be:
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src
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===
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* *
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**************************************************
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.. _amdgpu_synid_gfx90a_src_1:
|
||||
.. _amdgpu_synid_gfx90a_src_d578c4:
|
||||
|
||||
src
|
||||
===
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_src_4:
|
||||
.. _amdgpu_synid_gfx90a_src_d95796:
|
||||
|
||||
src
|
||||
===
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_src:
|
||||
.. _amdgpu_synid_gfx90a_src_e1561c:
|
||||
|
||||
src
|
||||
===
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_src_10:
|
||||
.. _amdgpu_synid_gfx90a_src_e5cc81:
|
||||
|
||||
src
|
||||
===
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_src_5:
|
||||
.. _amdgpu_synid_gfx90a_src_f73668:
|
||||
|
||||
src
|
||||
===
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_srsrc:
|
||||
.. _amdgpu_synid_gfx90a_srsrc_79ffcd:
|
||||
|
||||
srsrc
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_srsrc_1:
|
||||
.. _amdgpu_synid_gfx90a_srsrc_e73d16:
|
||||
|
||||
srsrc
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_ssrc_8:
|
||||
.. _amdgpu_synid_gfx90a_ssrc_4db4a9:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_ssrc_7:
|
||||
.. _amdgpu_synid_gfx90a_ssrc_57838b:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_ssrc_2:
|
||||
.. _amdgpu_synid_gfx90a_ssrc_595c25:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_ssrc_5:
|
||||
.. _amdgpu_synid_gfx90a_ssrc_65f041:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_ssrc_1:
|
||||
.. _amdgpu_synid_gfx90a_ssrc_aee59c:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_ssrc_4:
|
||||
.. _amdgpu_synid_gfx90a_ssrc_c31902:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_ssrc:
|
||||
.. _amdgpu_synid_gfx90a_ssrc_c5d631:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_ssrc_6:
|
||||
.. _amdgpu_synid_gfx90a_ssrc_c8a322:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_ssrc_3:
|
||||
.. _amdgpu_synid_gfx90a_ssrc_e9f591:
|
||||
|
||||
ssrc
|
||||
====
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vaddr_0212e3:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
A 64-bit flat global address or a 32-bit offset depending on addressing mode:
|
||||
|
||||
* Address = :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx90a_saddr_a37373>` set to :ref:`off<amdgpu_synid_off>`.
|
||||
* Address = :ref:`saddr<amdgpu_synid_gfx90a_saddr_a37373>` + :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_0212e3>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx90a_saddr_a37373>` is not :ref:`off<amdgpu_synid_off>`.
|
||||
|
||||
*Size:* 1 or 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vaddr_2:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
A 64-bit flat global address or a 32-bit offset depending on addressing mode:
|
||||
|
||||
* Address = :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid_gfx90a_saddr>` set to :ref:`off<amdgpu_synid_off>`.
|
||||
* Address = :ref:`saddr<amdgpu_synid_gfx90a_saddr>` + :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_2>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid_gfx90a_saddr>` is not :ref:`off<amdgpu_synid_off>`.
|
||||
|
||||
*Size:* 1 or 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vaddr_4:
|
||||
.. _amdgpu_synid_gfx90a_vaddr_5d0b42:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
|
@ -14,8 +14,8 @@ Image address which includes from one to four dimensional coordinates and other
|
|||
|
||||
*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode, specific image being handled and :ref:`a16<amdgpu_synid_a16>`.
|
||||
|
||||
Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
|
||||
Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
|
||||
|
||||
Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
|
||||
Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`
|
||||
|
|
@ -5,14 +5,14 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vaddr_3:
|
||||
.. _amdgpu_synid_gfx90a_vaddr_76b997:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
||||
An optional 32-bit flat scratch offset. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
|
||||
|
||||
Either this operand or :ref:`saddr<amdgpu_synid_gfx90a_saddr_1>` must be set to :ref:`off<amdgpu_synid_off>`.
|
||||
Either this operand or :ref:`saddr<amdgpu_synid_gfx90a_saddr_6060e5>` must be set to :ref:`off<amdgpu_synid_off>`.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vaddr_1:
|
||||
.. _amdgpu_synid_gfx90a_vaddr_9f7133:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vaddr_5:
|
||||
.. _amdgpu_synid_gfx90a_vaddr_b73dc0:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vaddr:
|
||||
.. _amdgpu_synid_gfx90a_vaddr_f20ee4:
|
||||
|
||||
vaddr
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata0_1:
|
||||
.. _amdgpu_synid_gfx90a_vdata0_9ad749:
|
||||
|
||||
vdata0
|
||||
======
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata0:
|
||||
.. _amdgpu_synid_gfx90a_vdata0_be4895:
|
||||
|
||||
vdata0
|
||||
======
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata1_1:
|
||||
.. _amdgpu_synid_gfx90a_vdata1_9ad749:
|
||||
|
||||
vdata1
|
||||
======
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata1:
|
||||
.. _amdgpu_synid_gfx90a_vdata1_be4895:
|
||||
|
||||
vdata1
|
||||
======
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_8:
|
||||
.. _amdgpu_synid_gfx90a_vdata_2a60db:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_9:
|
||||
.. _amdgpu_synid_gfx90a_vdata_2d0375:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_2:
|
||||
.. _amdgpu_synid_gfx90a_vdata_848ff7:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_10:
|
||||
.. _amdgpu_synid_gfx90a_vdata_8e9b87:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_7:
|
||||
.. _amdgpu_synid_gfx90a_vdata_929b59:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_1:
|
||||
.. _amdgpu_synid_gfx90a_vdata_9ad749:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_6:
|
||||
.. _amdgpu_synid_gfx90a_vdata_a5f23e:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_4:
|
||||
.. _amdgpu_synid_gfx90a_vdata_af2725:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -16,10 +16,10 @@ Optionally may serve as an output data:
|
|||
|
||||
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify 1 data element for 32-bit-per-pixel surfaces or 2 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
|
||||
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
|
||||
Note: the surface data format is indicated in the image resource constant but not in the instruction.
|
||||
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata:
|
||||
.. _amdgpu_synid_gfx90a_vdata_be4895:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_5:
|
||||
.. _amdgpu_synid_gfx90a_vdata_ca6e5f:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -16,10 +16,10 @@ Optionally may serve as an output data:
|
|||
|
||||
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`tfe<amdgpu_synid_tfe>`:
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify 2 data elements for 32-bit-per-pixel surfaces or 4 data elements for 64-bit-per-pixel surfaces. Each data element occupies 1 dword.
|
||||
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
|
||||
Note: the surface data format is indicated in the image resource constant but not in the instruction.
|
||||
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdata_3:
|
||||
.. _amdgpu_synid_gfx90a_vdata_cfb402:
|
||||
|
||||
vdata
|
||||
=====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_1:
|
||||
.. _amdgpu_synid_gfx90a_vdst_0f48d1:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_11:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 4 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_12:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
If :ref:`lds<amdgpu_synid_lds>` is specified, this operand is ignored by H/W and data are stored directly into LDS.
|
||||
|
||||
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
Note that :ref:`tfe<amdgpu_synid_tfe>` and :ref:`lds<amdgpu_synid_lds>` cannot be used together.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_2:
|
||||
.. _amdgpu_synid_gfx90a_vdst_180bef:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_3:
|
||||
.. _amdgpu_synid_gfx90a_vdst_260aca:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -5,13 +5,15 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_10:
|
||||
.. _amdgpu_synid_gfx90a_vdst_5258b4:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 3 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
This is an optional operand. It must be used if and only if :ref:`lds<amdgpu_synid_lds>` is omitted.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_16:
|
||||
.. _amdgpu_synid_gfx90a_vdst_69a144:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_13:
|
||||
.. _amdgpu_synid_gfx90a_vdst_78dd0a:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -5,17 +5,17 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_7:
|
||||
.. _amdgpu_synid_gfx90a_vdst_7c9848:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Image data to load by an image instruction.
|
||||
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
|
||||
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
|
||||
|
||||
* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
|
||||
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
|
||||
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_14:
|
||||
.. _amdgpu_synid_gfx90a_vdst_89680f:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_18:
|
||||
.. _amdgpu_synid_gfx90a_vdst_8c77d4:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -5,13 +5,13 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_8:
|
||||
.. _amdgpu_synid_gfx90a_vdst_a32035:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
*Size:* 4 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_15:
|
||||
.. _amdgpu_synid_gfx90a_vdst_bdb32f:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_19:
|
||||
.. _amdgpu_synid_gfx90a_vdst_c8d317:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_4:
|
||||
.. _amdgpu_synid_gfx90a_vdst_c8ee02:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_d0c0cb:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 1 dword.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_17:
|
||||
.. _amdgpu_synid_gfx90a_vdst_d6f4bd:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
..
|
||||
**************************************************
|
||||
* *
|
||||
* Automatically generated file, do not edit! *
|
||||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_d8236e:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 2 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
|
||||
|
|
@ -5,13 +5,13 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_9:
|
||||
.. _amdgpu_synid_gfx90a_vdst_e2898f:
|
||||
|
||||
vdst
|
||||
====
|
||||
|
||||
Instruction output: data read from a memory buffer.
|
||||
|
||||
*Size:* 2 dwords by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
|
||||
*Size:* 3 dwords.
|
||||
|
||||
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`a<amdgpu_synid_a>`
|
||||
|
|
@ -5,7 +5,7 @@
|
|||
* *
|
||||
**************************************************
|
||||
|
||||
.. _amdgpu_synid_gfx90a_vdst_5:
|
||||
.. _amdgpu_synid_gfx90a_vdst_ef6c94:
|
||||
|
||||
vdst
|
||||
====
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue