forked from OSchip/llvm-project
[VP] Add test to show optimization opportunities
Add vp.add test cases that can are optimized with D92086 to show the potential of generalized pattern rewriting. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D129746
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instsimplify -S | FileCheck %s
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declare <2 x i32> @llvm.vp.add.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
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declare <2 x i32> @llvm.vp.sub.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
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declare <2 x i8> @llvm.vp.add.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
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declare <2 x i8> @llvm.vp.sub.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
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; Constant folding should just work.
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define <2 x i32> @constant_vp_add(<2 x i1> %mask, i32 %evl) {
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; CHECK-LABEL: @constant_vp_add(
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; CHECK-NEXT: [[Q:%.*]] = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> <i32 3, i32 3>, <2 x i32> <i32 7, i32 7>, <2 x i1> [[MASK:%.*]], i32 [[EVL:%.*]])
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; CHECK-NEXT: ret <2 x i32> [[Q]]
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;
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%Q = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> <i32 3, i32 3>, <2 x i32> <i32 7, i32 7>, <2 x i1> %mask, i32 %evl)
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ret <2 x i32> %Q
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}
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; Simplifying pure VP intrinsic patterns.
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define <2 x i32> @common_sub_operand(<2 x i32> %X, <2 x i32> %Y, <2 x i1> %mask, i32 %evl) {
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; CHECK-LABEL: @common_sub_operand(
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; CHECK-NEXT: [[Z:%.*]] = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.*]])
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; CHECK-NEXT: [[Q:%.*]] = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> [[Z]], <2 x i32> [[Y]], <2 x i1> [[MASK]], i32 [[EVL]])
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; CHECK-NEXT: ret <2 x i32> [[Q]]
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;
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; %Z = sub i32 %X, %Y, vp(%mask, %evl)
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%Z = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %X, <2 x i32> %Y, <2 x i1> %mask, i32 %evl)
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; %Q = add i32 %Z, %Y, vp(%mask, %evl)
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%Q = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %Z, <2 x i32> %Y, <2 x i1> %mask, i32 %evl)
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ret <2 x i32> %Q
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}
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; Mixing regular SIMD with vp intrinsics (vp add match root).
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define <2 x i32> @common_sub_operand_vproot(<2 x i32> %X, <2 x i32> %Y, <2 x i1> %mask, i32 %evl) {
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; CHECK-LABEL: @common_sub_operand_vproot(
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; CHECK-NEXT: [[Z:%.*]] = sub <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[Q:%.*]] = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> [[Z]], <2 x i32> [[Y]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.*]])
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; CHECK-NEXT: ret <2 x i32> [[Q]]
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;
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%Z = sub <2 x i32> %X, %Y
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; %Q = add i32 %Z, %Y, vp(%mask, %evl)
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%Q = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %Z, <2 x i32> %Y, <2 x i1> %mask, i32 %evl)
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ret <2 x i32> %Q
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}
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; Mixing regular SIMD with vp intrinsics (vp inside pattern, regular instruction root).
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define <2 x i32> @common_sub_operand_vpinner(<2 x i32> %X, <2 x i32> %Y, <2 x i1> %mask, i32 %evl) {
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; CHECK-LABEL: @common_sub_operand_vpinner(
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; CHECK-NEXT: [[Z:%.*]] = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.*]])
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; CHECK-NEXT: [[Q:%.*]] = add <2 x i32> [[Z]], [[Y]]
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; CHECK-NEXT: ret <2 x i32> [[Q]]
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;
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; %Z = sub i32 %X, %Y, vp(%mask, %evl)
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%Z = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %X, <2 x i32> %Y, <2 x i1> %mask, i32 %evl)
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%Q = add <2 x i32> %Z, %Y
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ret <2 x i32> %Q
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}
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define <2 x i32> @negated_operand(<2 x i32> %x, <2 x i1> %mask, i32 %evl) {
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; CHECK-LABEL: @negated_operand(
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; CHECK-NEXT: [[NEGX:%.*]] = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> zeroinitializer, <2 x i32> [[X:%.*]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.*]])
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; CHECK-NEXT: [[R:%.*]] = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> [[NEGX]], <2 x i32> [[X]], <2 x i1> [[MASK]], i32 [[EVL]])
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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; %negx = sub i32 0, %x
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%negx = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> zeroinitializer, <2 x i32> %x, <2 x i1> %mask, i32 %evl)
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; %r = add i32 %negx, %x
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%r = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %negx, <2 x i32> %x, <2 x i1> %mask, i32 %evl)
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ret <2 x i32> %r
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}
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; TODO Lift InstSimplify::SimplifyAdd to the trait framework to optimize this.
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define <2 x i8> @knownnegation(<2 x i8> %x, <2 x i8> %y, <2 x i1> %mask, i32 %evl) {
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; TODO-CHECK-LABEL: @knownnegation(
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; TODO-XHECK-NEXT: ret i8 <2 x i8> zeroinitializer
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;
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; %xy = sub i8 %x, %y
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; CHECK-LABEL: @knownnegation(
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; CHECK-NEXT: [[XY:%.*]] = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]], <2 x i1> [[MASK:%.*]], i32 [[EVL:%.*]])
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; CHECK-NEXT: [[YX:%.*]] = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> [[Y]], <2 x i8> [[X]], <2 x i1> [[MASK]], i32 [[EVL]])
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; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> [[XY]], <2 x i8> [[YX]], <2 x i1> [[MASK]], i32 [[EVL]])
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; CHECK-NEXT: ret <2 x i8> [[R]]
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;
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%xy = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %x, <2 x i8> %y, <2 x i1> %mask, i32 %evl)
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; %yx = sub i8 %y, %x
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%yx = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %y, <2 x i8> %x, <2 x i1> %mask, i32 %evl)
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; %r = add i8 %xy, %yx
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%r = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %xy, <2 x i8> %yx, <2 x i1> %mask, i32 %evl)
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ret <2 x i8> %r
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}
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