forked from OSchip/llvm-project
[AArch64][SVE]Add cost model for vector reduce for scalable vector
This patch computes the cost for vector.reduce<operand> for scalable vectors. The cost is split into two parts: the legalization cost and the horizontal reduction. Differential Revision: https://reviews.llvm.org/D93639
This commit is contained in:
Caroline Concatto
parent
b7e516202e
commit
172f1f8952
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@ -1288,15 +1288,11 @@ public:
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case Intrinsic::vector_reduce_fmin:
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case Intrinsic::vector_reduce_fmin:
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case Intrinsic::vector_reduce_umax:
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case Intrinsic::vector_reduce_umax:
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case Intrinsic::vector_reduce_umin: {
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case Intrinsic::vector_reduce_umin: {
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if (isa<ScalableVectorType>(RetTy))
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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IntrinsicCostAttributes Attrs(IID, RetTy, Args[0]->getType(), FMF, 1, I);
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IntrinsicCostAttributes Attrs(IID, RetTy, Args[0]->getType(), FMF, 1, I);
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return getTypeBasedIntrinsicInstrCost(Attrs, CostKind);
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return getTypeBasedIntrinsicInstrCost(Attrs, CostKind);
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}
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}
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case Intrinsic::vector_reduce_fadd:
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case Intrinsic::vector_reduce_fadd:
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case Intrinsic::vector_reduce_fmul: {
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case Intrinsic::vector_reduce_fmul: {
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if (isa<ScalableVectorType>(RetTy))
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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IntrinsicCostAttributes Attrs(
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IntrinsicCostAttributes Attrs(
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IID, RetTy, {Args[0]->getType(), Args[1]->getType()}, FMF, 1, I);
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IID, RetTy, {Args[0]->getType(), Args[1]->getType()}, FMF, 1, I);
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return getTypeBasedIntrinsicInstrCost(Attrs, CostKind);
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return getTypeBasedIntrinsicInstrCost(Attrs, CostKind);
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@ -1096,11 +1096,70 @@ bool AArch64TTIImpl::useReductionIntrinsic(unsigned Opcode, Type *Ty,
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return false;
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return false;
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}
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}
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int AArch64TTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
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bool IsPairwise, bool IsUnsigned,
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TTI::TargetCostKind CostKind) {
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if (!isa<ScalableVectorType>(Ty))
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return BaseT::getMinMaxReductionCost(Ty, CondTy, IsPairwise, IsUnsigned,
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CostKind);
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assert((isa<ScalableVectorType>(Ty) && isa<ScalableVectorType>(CondTy)) &&
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"Both vector needs to be scalable");
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std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
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int LegalizationCost = 0;
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if (LT.first > 1) {
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Type *LegalVTy = EVT(LT.second).getTypeForEVT(Ty->getContext());
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unsigned CmpOpcode =
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Ty->isFPOrFPVectorTy() ? Instruction::FCmp : Instruction::ICmp;
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LegalizationCost =
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getCmpSelInstrCost(CmpOpcode, LegalVTy, LegalVTy,
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CmpInst::BAD_ICMP_PREDICATE, CostKind) +
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getCmpSelInstrCost(Instruction::Select, LegalVTy, LegalVTy,
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CmpInst::BAD_ICMP_PREDICATE, CostKind);
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LegalizationCost *= LT.first - 1;
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}
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return LegalizationCost + /*Cost of horizontal reduction*/ 2;
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}
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int AArch64TTIImpl::getArithmeticReductionCostSVE(
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unsigned Opcode, VectorType *ValTy, bool IsPairwise,
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TTI::TargetCostKind CostKind) {
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assert(!IsPairwise && "Cannot be pair wise to continue");
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std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
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int LegalizationCost = 0;
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if (LT.first > 1) {
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Type *LegalVTy = EVT(LT.second).getTypeForEVT(ValTy->getContext());
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LegalizationCost = getArithmeticInstrCost(Opcode, LegalVTy, CostKind);
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LegalizationCost *= LT.first - 1;
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}
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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// Add the final reduction cost for the legal horizontal reduction
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switch (ISD) {
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case ISD::ADD:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::FADD:
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return LegalizationCost + 2;
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default:
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// TODO: Replace for invalid when InstructionCost is used
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// cases not supported by SVE
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return 16;
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}
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}
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int AArch64TTIImpl::getArithmeticReductionCost(unsigned Opcode,
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int AArch64TTIImpl::getArithmeticReductionCost(unsigned Opcode,
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VectorType *ValTy,
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VectorType *ValTy,
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bool IsPairwiseForm,
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bool IsPairwiseForm,
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TTI::TargetCostKind CostKind) {
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TTI::TargetCostKind CostKind) {
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if (isa<ScalableVectorType>(ValTy))
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return getArithmeticReductionCostSVE(Opcode, ValTy, IsPairwiseForm,
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CostKind);
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if (IsPairwiseForm)
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if (IsPairwiseForm)
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return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwiseForm,
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return BaseT::getArithmeticReductionCost(Opcode, ValTy, IsPairwiseForm,
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CostKind);
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CostKind);
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@ -139,6 +139,14 @@ public:
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int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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int getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
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bool IsPairwise, bool IsUnsigned,
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TTI::TargetCostKind CostKind);
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int getArithmeticReductionCostSVE(unsigned Opcode, VectorType *ValTy,
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bool IsPairwiseForm,
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TTI::TargetCostKind CostKind);
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int getArithmeticInstrCost(
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int getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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unsigned Opcode, Type *Ty,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
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@ -0,0 +1,251 @@
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; Check getIntrinsicInstrCost in BasicTTIImpl.h with SVE for vector.reduce.<operand>
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; Checks legal and not legal vector size
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; RUN: opt -cost-model -analyze -mtriple=aarch64--linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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define i32 @add.i32.nxv4i32(<vscale x 4 x i32> %v) {
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; CHECK-LABEL: 'add.i32.nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)
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; CHECK-NEXT:Cost Model: Found an estimated cost of 0 for instruction: ret i32 %r
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%r = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)
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ret i32 %r
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}
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define i64 @add.i64.nxv4i64(<vscale x 4 x i64> %v) {
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; CHECK-LABEL: 'add.i64.nxv4i64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
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; CHECK-NEXT:Cost Model: Found an estimated cost of 0 for instruction: ret i64 %r
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%r = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
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ret i64 %r
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}
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define i32 @mul.i32.nxv4i32(<vscale x 4 x i32> %v) {
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; CHECK-LABEL: 'mul.i32.nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %r
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%r = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %v)
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ret i32 %r
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}
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define i64 @mul.i64.nxv4i64(<vscale x 4 x i64> %v) {
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; CHECK-LABEL: 'mul.i64.nxv4i64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %r = call i64 @llvm.vector.reduce.mul.nxv4i64(<vscale x 4 x i64> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %r
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%r = call i64 @llvm.vector.reduce.mul.nxv4i64(<vscale x 4 x i64> %v)
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ret i64 %r
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}
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define i32 @and.i32.nxv4i32(<vscale x 4 x i32> %v) {
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; CHECK-LABEL: 'and.i32.nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %r
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%r = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)
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ret i32 %r
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}
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define i64 @and.i64.nxv4i64(<vscale x 4 x i64> %v) {
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; CHECK-LABEL: 'and.i64.nxv4i64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %r
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%r = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
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ret i64 %r
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}
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define i32 @or.i32.nxv4i32(<vscale x 4 x i32> %v) {
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; CHECK-LABEL: 'or.i32.nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %r
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%r = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)
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ret i32 %r
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}
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define i64 @or.i64.nxv4i64(<vscale x 4 x i64> %v) {
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; CHECK-LABEL: 'or.i64.nxv4i64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %r
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%r = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
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ret i64 %r
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}
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define i32 @xor.i32.nxv4i32(<vscale x 4 x i32> %v) {
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; CHECK-LABEL: 'xor.i32.nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %r
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%r = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)
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ret i32 %r
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}
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define i64 @xor.i64.nxv4i64(<vscale x 4 x i64> %v) {
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; CHECK-LABEL: 'xor.i64.nxv4i64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %r = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %r
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%r = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
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ret i64 %r
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}
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define i32 @umin.i32.nxv4i32(<vscale x 4 x i32> %v) {
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; CHECK-LABEL: 'umin.i32.nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %r
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%r = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)
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ret i32 %r
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}
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define i64 @umin.i64.nxv4i64(<vscale x 4 x i64> %v) {
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; CHECK-LABEL: 'umin.i64.nxv4i64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %r
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%r = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
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ret i64 %r
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}
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define float @fmax.f32.nxv4f32(<vscale x 4 x float> %v) {
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; CHECK-LABEL: 'fmax.f32.nxv4f32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret float %r
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%r = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v)
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ret float %r
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}
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define double @fmax.f64.nxv4f64(<vscale x 4 x double> %v) {
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; CHECK-LABEL: 'fmax.f64.nxv4f64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret double %r
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%r = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v)
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ret double %r
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}
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define float @fmin.f32.nxv4f32(<vscale x 4 x float> %v) {
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; CHECK-LABEL: 'fmin.f32.nxv4f32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret float %r
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%r = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v)
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ret float %r
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}
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define double @fmin.f64.nxv4f64(<vscale x 4 x double> %v) {
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; CHECK-LABEL: 'fmin.f64.nxv4f64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret double %r
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%r = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v)
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ret double %r
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}
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define i32 @umax.i32.nxv4i32(<vscale x 4 x i32> %v) {
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; CHECK-LABEL: 'umax.i32.nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %r
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%r = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)
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ret i32 %r
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}
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define i64 @umax.i64.nxv4i64(<vscale x 4 x i64> %v) {
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; CHECK-LABEL: 'umax.i64.nxv4i64'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %r
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%r = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
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ret i64 %r
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}
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define i32 @smin.i32.nxv4i32(<vscale x 4 x i32> %v) {
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; CHECK-LABEL: 'smin.i32.nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %r
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%r = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)
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ret i32 %r
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}
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||||||
|
define i64 @smin.i64.nxv4i64(<vscale x 4 x i64> %v) {
|
||||||
|
; CHECK-LABEL: 'smin.i64.nxv4i64'
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %r
|
||||||
|
|
||||||
|
%r = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
|
||||||
|
ret i64 %r
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @smax.i32.nxv4i32(<vscale x 4 x i32> %v) {
|
||||||
|
; CHECK-LABEL: 'smax.i32.nxv4i32'
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %r = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 %r
|
||||||
|
|
||||||
|
%r = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)
|
||||||
|
ret i32 %r
|
||||||
|
}
|
||||||
|
|
||||||
|
define i64 @smax.i64.nxv4i64(<vscale x 4 x i64> %v) {
|
||||||
|
; CHECK-LABEL: 'smax.i64.nxv4i64'
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %r = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i64 %r
|
||||||
|
|
||||||
|
%r = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
|
||||||
|
ret i64 %r
|
||||||
|
}
|
||||||
|
|
||||||
|
define float @fadda_nxv4f32(float %start, <vscale x 4 x float> %a) #0 {
|
||||||
|
; CHECK-LABEL: 'fadda_nxv4f32
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res = call float @llvm.vector.reduce.fadd.nxv4f32(float %start, <vscale x 4 x float> %a)
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret float %res
|
||||||
|
|
||||||
|
%res = call float @llvm.vector.reduce.fadd.nxv4f32(float %start, <vscale x 4 x float> %a)
|
||||||
|
ret float %res
|
||||||
|
}
|
||||||
|
|
||||||
|
define double @fadda_nxv4f64(double %start, <vscale x 4 x double> %a) #0 {
|
||||||
|
; CHECK-LABEL: 'fadda_nxv4f64
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %res = call double @llvm.vector.reduce.fadd.nxv4f64(double %start, <vscale x 4 x double> %a)
|
||||||
|
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret double %res
|
||||||
|
|
||||||
|
%res = call double @llvm.vector.reduce.fadd.nxv4f64(double %start, <vscale x 4 x double> %a)
|
||||||
|
ret double %res
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float>)
|
||||||
|
declare float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float>)
|
||||||
|
declare i32 @llvm.vector.reduce.fmin.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32>)
|
||||||
|
declare float @llvm.vector.reduce.fadd.nxv4f32(float, <vscale x 4 x float>)
|
||||||
|
declare i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64>)
|
||||||
|
declare i64 @llvm.vector.reduce.mul.nxv4i64(<vscale x 4 x i64>)
|
||||||
|
declare i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64>)
|
||||||
|
declare i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64>)
|
||||||
|
declare i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64>)
|
||||||
|
declare double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double>)
|
||||||
|
declare double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double>)
|
||||||
|
declare i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64>)
|
||||||
|
declare i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64>)
|
||||||
|
declare i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64>)
|
||||||
|
declare i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64>)
|
||||||
|
declare double @llvm.vector.reduce.fadd.nxv4f64(double, <vscale x 4 x double>)
|
||||||
Loading…
Reference in New Issue