forked from OSchip/llvm-project
[AArch64][SVE2] Minor refactoring and cleanup
Summary: * Clarify comment with SVE2 for predicated shifts and move next to other shift instructions. * Clarify comments for various instructions. * Move FCVTX instruction next to other fp conversions. * Move FLOGB to next to other fp instructions and fix description. * Remove "cons" from non-constructive multiclass for bitwise shift-right and accumulate instructions. Reviewed By: sdesmalen Differential Revision: https://reviews.llvm.org/D65390 llvm-svn: 367396
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Cullen Rhodes
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@ -1164,6 +1164,13 @@ let Predicates = [HasSVE2] in {
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defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr">;
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defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr">;
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// SVE2 predicated shifts
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defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
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defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
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defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
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defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
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defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
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// SVE2 integer add/subtract long
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defm SADDLB_ZZZ : sve2_wide_int_arith_long<0b00000, "saddlb">;
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defm SADDLT_ZZZ : sve2_wide_int_arith_long<0b00001, "saddlt">;
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@ -1203,10 +1210,10 @@ let Predicates = [HasSVE2] in {
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defm SLI_ZZI : sve2_int_bin_shift_imm_left< 0b1, "sli">;
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// SVE2 bitwise shift right and accumulate
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defm SSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b00, "ssra">;
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defm USRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b01, "usra">;
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defm SRSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b10, "srsra">;
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defm URSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b11, "ursra">;
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defm SSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b00, "ssra">;
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defm USRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b01, "usra">;
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defm SRSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b10, "srsra">;
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defm URSRA_ZZI : sve2_int_bin_accum_shift_imm_right<0b11, "ursra">;
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// SVE2 complex integer add
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defm CADD_ZZI : sve2_int_cadd<0b0, "cadd">;
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@ -1295,10 +1302,14 @@ let Predicates = [HasSVE2] in {
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// SVE2 histogram generation (vector)
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defm HISTCNT_ZPzZZ : sve2_hist_gen_vector<"histcnt">;
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// SVE2 floating-point base 2 logarithm as integer
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defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">;
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// SVE2 floating-point convert precision
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defm FCVTXNT_ZPmZ : sve2_fp_convert_down_odd_rounding<"fcvtxnt">;
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defm FCVTNT_ZPmZ : sve2_fp_convert_down_narrow<"fcvtnt">;
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defm FCVTLT_ZPmZ : sve2_fp_convert_up_long<"fcvtlt">;
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def FCVTX_ZPmZ_DtoS : sve_fp_2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32, ElementSizeD>;
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// SVE2 floating-point pairwise operations
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defm FADDP_ZPmZZ : sve2_fp_pairwise_pred<0b000, "faddp">;
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@ -1327,17 +1338,12 @@ let Predicates = [HasSVE2] in {
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def BSL2N_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b101, "bsl2n">;
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def NBSL_ZZZZ_D : sve2_int_bitwise_ternary_op_d<0b111, "nbsl">;
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// sve_int_rotate_imm
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// SVE2 bitwise xor and rotate right by immediate
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defm XAR_ZZZI : sve2_int_rotate_right_imm<"xar">;
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// SVE2 extract vector (immediate offset, constructive)
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def EXT_ZZI_B : sve2_int_perm_extract_i_cons<"ext">;
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// SVE floating-point convert precision
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def FCVTX_ZPmZ_DtoS : sve_fp_2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32, ElementSizeD>;
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// SVE floating-point convert to integer
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defm FLOGB_ZPmZ : sve2_fp_flogb<"flogb">;
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// Non-temporal contiguous loads (vector + register)
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defm LDNT1SB_ZZR_S : sve2_mem_cldnt_vs<0b00000, "ldnt1sb", Z_s, ZPR32>;
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@ -1357,12 +1363,6 @@ let Predicates = [HasSVE2] in {
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// SVE2 vector splice (constructive)
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defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice">;
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// Predicated shifts
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defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
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defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
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defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
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defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
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defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
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// Non-temporal contiguous stores (vector + register)
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defm STNT1B_ZZR_S : sve2_mem_cstnt_vs<0b001, "stnt1b", Z_s, ZPR32>;
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@ -1374,11 +1374,11 @@ let Predicates = [HasSVE2] in {
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defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>;
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defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>;
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// SVE table lookup (three sources)
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// SVE2 table lookup (three sources)
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defm TBL_ZZZZ : sve2_int_perm_tbl<"tbl">;
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defm TBX_ZZZ : sve2_int_perm_tbx<"tbx">;
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// SVE integer compare scalar count and limit
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// SVE2 integer compare scalar count and limit
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defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege">;
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defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt">;
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defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs">;
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@ -1389,7 +1389,7 @@ let Predicates = [HasSVE2] in {
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defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs">;
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defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi">;
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// SVE pointer conflict compare
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// SVE2 pointer conflict compare
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defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr">;
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defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw">;
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}
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@ -2530,8 +2530,8 @@ multiclass sve2_int_bin_shift_imm_right<bit opc, string asm> {
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}
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}
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class sve2_int_bin_accum_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm,
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ZPRRegOp zprty, Operand immtype>
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class sve2_int_bin_accum_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm,
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ZPRRegOp zprty, Operand immtype>
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: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, immtype:$imm),
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asm, "\t$Zda, $Zn, $imm",
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"", []>, Sched<[]> {
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@ -2553,15 +2553,15 @@ class sve2_int_bin_accum_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm
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let ElementSize = ElementSizeNone;
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}
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multiclass sve2_int_bin_accum_cons_shift_imm_right<bits<2> opc, string asm> {
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def _B : sve2_int_bin_accum_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
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def _H : sve2_int_bin_accum_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
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multiclass sve2_int_bin_accum_shift_imm_right<bits<2> opc, string asm> {
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def _B : sve2_int_bin_accum_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
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def _H : sve2_int_bin_accum_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
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let Inst{19} = imm{3};
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}
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def _S : sve2_int_bin_accum_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
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def _S : sve2_int_bin_accum_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
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let Inst{20-19} = imm{4-3};
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}
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def _D : sve2_int_bin_accum_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
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def _D : sve2_int_bin_accum_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
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let Inst{22} = imm{5};
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let Inst{20-19} = imm{4-3};
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}
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