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[RISCV] Preserve fast math flags in lowerVPOp. 

Update test to check MIR after finalize-isel instead of debug output.

This is of course not the only place we should preserve FMF, but
it's the most obvious one.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D126306
This commit is contained in:
Craig Topper 2022-05-25 09:16:07 -07:00
parent 06fee478d2
commit 172149e98c
3 changed files with 26 additions and 11 deletions
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4
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -6055,11 +6055,11 @@ SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG,
}
if (!VT.isFixedLengthVector())
return DAG.getNode(RISCVISDOpc, DL, VT, Ops);
return DAG.getNode(RISCVISDOpc, DL, VT, Ops, Op->getFlags());
MVT ContainerVT = getContainerForFixedLengthVector(VT);
SDValue VPOp = DAG.getNode(RISCVISDOpc, DL, ContainerVT, Ops);
SDValue VPOp = DAG.getNode(RISCVISDOpc, DL, ContainerVT, Ops, Op->getFlags());
return convertFromScalableVector(VT, VPOp, DAG, Subtarget);
}

9
llvm/test/CodeGen/RISCV/pass-fast-math-flags-sdnode.ll
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@ -1,9 +0,0 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -debug-only=isel -o /dev/null 2>&1 | FileCheck %s
declare <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)
define <vscale x 1 x double> @foo(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x double> %z, <vscale x 1 x i1> %m, i32 %vl) {
; CHECK: t14: nxv1f64 = vp_fmul nnan ninf nsz arcp contract afn reassoc t2, t4, t8, t13
%1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)
ret <vscale x 1 x double> %1
}

24
llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll Normal file
View File

@ -0,0 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel | FileCheck %s
declare <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)
define <vscale x 1 x double> @foo(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x double> %z, <vscale x 1 x i1> %m, i32 %vl) {
; CHECK-LABEL: name: foo
; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $v8, $v9, $v0, $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gprnox0 = SRLI killed [[SLLI]], 32
; CHECK-NEXT: $v0 = COPY [[COPY1]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
; CHECK-NEXT: %7:vrnov0 = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFMUL_VV_M1_MASK [[DEF]], [[COPY3]], [[COPY2]], $v0, killed [[SRLI]], 6 /* e64 */, 1, implicit $frm
; CHECK-NEXT: $v8 = COPY %7
; CHECK-NEXT: PseudoRET implicit $v8
%1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)
ret <vscale x 1 x double> %1
}