diff --git a/llvm/include/llvm/Target/TargetSubtarget.h b/llvm/include/llvm/Target/TargetSubtarget.h index 14f612af9794..ac094f664419 100644 --- a/llvm/include/llvm/Target/TargetSubtarget.h +++ b/llvm/include/llvm/Target/TargetSubtarget.h @@ -39,10 +39,14 @@ public: /// should be attempted. virtual unsigned getSpecialAddressLatency() const { return 0; } + // enablePostRAScheduler - Return true to enable + // post-register-allocation scheduling. + virtual bool enablePostRAScheduler() const { return false; } + // adjustSchedDependency - Perform target specific adjustments to // the latency of a schedule dependency. virtual void adjustSchedDependency(SUnit *def, SUnit *use, - SDep& dep) const { }; + SDep& dep) const { } }; } // End llvm namespace diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index 64e28fb764f5..a38d8ccab782 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -45,14 +45,6 @@ static cl::opt VerifyMachineCode("verify-machineinstrs", cl::Hidden, cl::desc("Verify generated machine code"), cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL)); -// This is not enabled by default due to 1) high compile time cost, 2) it's not -// beneficial to all targets. The plan is to let targets decide whether this -// is enabled. -static cl::opt -EnablePostRAScheduler("post-RA-scheduler", - cl::desc("Enable scheduling after register allocation"), - cl::init(false)); - // Enable or disable FastISel. Both options are needed, because // FastISel is enabled by default with -fast, and we wish to be // able to enable or disable fast-isel independently from -O0. @@ -326,7 +318,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, printAndVerify(PM); // Second pass scheduler. - if (OptLevel != CodeGenOpt::None && EnablePostRAScheduler) { + if (OptLevel != CodeGenOpt::None) { PM.add(createPostRAScheduler()); printAndVerify(PM); } diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 9d75b25b82c7..42954eac4f6d 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -34,6 +34,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Target/TargetSubtarget.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -209,6 +210,11 @@ static bool isSchedulingBoundary(const MachineInstr *MI, } bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { + // Check that post-RA scheduling is enabled for this function + const TargetSubtarget &ST = Fn.getTarget().getSubtarget(); + if (!ST.enablePostRAScheduler()) + return true; + DEBUG(errs() << "PostRAScheduler\n"); const MachineLoopInfo &MLI = getAnalysis(); diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 8069e2b6a851..4174899dc095 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -43,6 +43,9 @@ def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", "true", "Use NEON for single-precision FP">; +def FeaturePostRASched : SubtargetFeature<"postrasched", "PostRAScheduler", + "true", + "Use Post-Register-Allocation Scheduler">; //===----------------------------------------------------------------------===// // ARM Processors supported. @@ -105,7 +108,8 @@ def : ProcNoItin<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>; // V7 Processors. def : Processor<"cortex-a8", CortexA8Itineraries, - [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>; + [ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP, + FeaturePostRASched]>; def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index f5723ea5618e..b46bd0c1b80f 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -29,6 +29,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, , UseNEONForSinglePrecisionFP(false) , IsThumb(isThumb) , ThumbMode(Thumb1) + , PostRAScheduler(false) , IsR9Reserved(ReserveR9) , stackAlignment(4) , CPUString("generic") diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index 518967b92430..7098fd4f36ba 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -55,6 +55,9 @@ protected: /// ThumbMode - Indicates supported Thumb version. ThumbTypeEnum ThumbMode; + /// PostRAScheduler - True if using post-register-allocation scheduler. + bool PostRAScheduler; + /// IsR9Reserved - True if R9 is a not available as general purpose register. bool IsR9Reserved; @@ -122,6 +125,10 @@ protected: bool isR9Reserved() const { return IsR9Reserved; } const std::string & getCPUString() const { return CPUString; } + + /// enablePostRAScheduler - From TargetSubtarget, return true to + /// enable post-RA scheduler. + bool enablePostRAScheduler() const { return PostRAScheduler; } /// getInstrItins - Return the instruction itineraies based on subtarget /// selection. diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll index 666f00256a71..49cde25265f9 100644 --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -post-RA-scheduler +; RUN: llc < %s -march=arm -mattr=+vfp2,+postrasched -mcpu=cortex-a8 ; ModuleID = '' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll index a21ffc38d09e..5c55ad2abc5c 100644 --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler +; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched ; ModuleID = '' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll index e3d8ea60f992..dacb7478c6fc 100644 --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler +; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched ; ModuleID = '' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" diff --git a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll index 9123377e7151..d497d1c88436 100644 --- a/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll +++ b/llvm/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler +; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched ; ModuleID = '' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" diff --git a/llvm/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll b/llvm/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll index 508ff5e43453..438073b61757 100644 --- a/llvm/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll +++ b/llvm/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll @@ -1,5 +1,5 @@ ; XFAIL: * -; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler | FileCheck %s +; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched | FileCheck %s ; ModuleID = ''