forked from OSchip/llvm-project
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
llvm-svn: 83122
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@ -39,10 +39,14 @@ public:
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/// should be attempted.
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virtual unsigned getSpecialAddressLatency() const { return 0; }
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// enablePostRAScheduler - Return true to enable
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// post-register-allocation scheduling.
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virtual bool enablePostRAScheduler() const { return false; }
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// adjustSchedDependency - Perform target specific adjustments to
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// the latency of a schedule dependency.
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virtual void adjustSchedDependency(SUnit *def, SUnit *use,
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SDep& dep) const { };
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SDep& dep) const { }
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};
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} // End llvm namespace
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@ -45,14 +45,6 @@ static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
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cl::desc("Verify generated machine code"),
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cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
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// This is not enabled by default due to 1) high compile time cost, 2) it's not
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// beneficial to all targets. The plan is to let targets decide whether this
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// is enabled.
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static cl::opt<bool>
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EnablePostRAScheduler("post-RA-scheduler",
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cl::desc("Enable scheduling after register allocation"),
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cl::init(false));
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// Enable or disable FastISel. Both options are needed, because
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// FastISel is enabled by default with -fast, and we wish to be
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// able to enable or disable fast-isel independently from -O0.
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@ -326,7 +318,7 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
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printAndVerify(PM);
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// Second pass scheduler.
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if (OptLevel != CodeGenOpt::None && EnablePostRAScheduler) {
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if (OptLevel != CodeGenOpt::None) {
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PM.add(createPostRAScheduler());
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printAndVerify(PM);
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}
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@ -34,6 +34,7 @@
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtarget.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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@ -209,6 +210,11 @@ static bool isSchedulingBoundary(const MachineInstr *MI,
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}
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bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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// Check that post-RA scheduling is enabled for this function
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const TargetSubtarget &ST = Fn.getTarget().getSubtarget<TargetSubtarget>();
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if (!ST.enablePostRAScheduler())
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return true;
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DEBUG(errs() << "PostRAScheduler\n");
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const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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@ -43,6 +43,9 @@ def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
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def FeatureNEONFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single-precision FP">;
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def FeaturePostRASched : SubtargetFeature<"postrasched", "PostRAScheduler",
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"true",
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"Use Post-Register-Allocation Scheduler">;
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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@ -105,7 +108,8 @@ def : ProcNoItin<"arm1156t2f-s", [ArchV6T2, FeatureThumb2, FeatureVFP2]>;
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// V7 Processors.
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def : Processor<"cortex-a8", CortexA8Itineraries,
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[ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP]>;
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[ArchV7A, FeatureThumb2, FeatureNEON, FeatureNEONFP,
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FeaturePostRASched]>;
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def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
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//===----------------------------------------------------------------------===//
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@ -29,6 +29,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
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, UseNEONForSinglePrecisionFP(false)
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, IsThumb(isThumb)
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, ThumbMode(Thumb1)
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, PostRAScheduler(false)
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, IsR9Reserved(ReserveR9)
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, stackAlignment(4)
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, CPUString("generic")
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@ -55,6 +55,9 @@ protected:
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/// ThumbMode - Indicates supported Thumb version.
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ThumbTypeEnum ThumbMode;
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/// PostRAScheduler - True if using post-register-allocation scheduler.
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bool PostRAScheduler;
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/// IsR9Reserved - True if R9 is a not available as general purpose register.
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bool IsR9Reserved;
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@ -122,6 +125,10 @@ protected:
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bool isR9Reserved() const { return IsR9Reserved; }
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const std::string & getCPUString() const { return CPUString; }
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/// enablePostRAScheduler - From TargetSubtarget, return true to
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/// enable post-RA scheduler.
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bool enablePostRAScheduler() const { return PostRAScheduler; }
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/// getInstrItins - Return the instruction itineraies based on subtarget
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/// selection.
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -post-RA-scheduler
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; RUN: llc < %s -march=arm -mattr=+vfp2,+postrasched -mcpu=cortex-a8
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; ModuleID = '<stdin>'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
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@ -1,4 +1,4 @@
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; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
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; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
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; ModuleID = '<stdin>'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
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@ -1,4 +1,4 @@
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; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
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; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
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; ModuleID = '<stdin>'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
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@ -1,4 +1,4 @@
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; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler
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; RUN: llc < %s -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched
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; ModuleID = '<stdin>'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
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@ -1,5 +1,5 @@
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; XFAIL: *
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; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler | FileCheck %s
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; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+postrasched | FileCheck %s
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; ModuleID = '<stdin>'
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