forked from OSchip/llvm-project
[X86] Add '.s' aliases to the assembler for the various redundant move encodings to match gas and our EVEX instructions.
We already have these aliases for EVEX enocded instructions, but not for the GPR, MMX, SSE, and VEX versions. Also remove the vpextrw.s EVEX alias. That's not something gas implements. llvm-svn: 334922
This commit is contained in:
Craig Topper
parent
49c9d8b849
commit
16fdde5e63
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@ -10601,9 +10601,6 @@ defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>, VEX_WIG;
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defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
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defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
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def : InstAlias<"vpextrw.s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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(VPEXTRWZrr_REV GR32orGR64:$dst, VR128X:$src1, u8imm:$src2), 0>;
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multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, PatFrag LdFrag> {
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def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
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@ -1652,6 +1652,24 @@ def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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FoldGenData<"MOV64rr">;
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}
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// Reversed version with ".s" suffix for GAS compatibility.
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def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}",
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(MOV8rr_REV GR8:$dst, GR8:$src), 0>;
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def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}",
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(MOV16rr_REV GR16:$dst, GR16:$src), 0>;
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def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}",
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(MOV32rr_REV GR32:$dst, GR32:$src), 0>;
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def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}",
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(MOV64rr_REV GR64:$dst, GR64:$src), 0>;
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def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
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(MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">;
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def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
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(MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">;
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def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
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(MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">;
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def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}",
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(MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">;
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let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
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def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
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"mov{b}\t{$src, $dst|$dst, $src}",
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@ -206,9 +206,6 @@ def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst),
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(ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}",
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[]>, Sched<[SchedWriteVecMoveLS.MMX.RM]>;
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// These are 64 bit moves, but since the OS X assembler doesn't
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// recognize a register-register movq, we write them as
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// movd.
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let isBitcast = 1 in {
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def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
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(outs GR64:$dst), (ins VR64:$src),
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@ -225,6 +222,9 @@ def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
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} // SchedRW, hasSideEffects, isMoveReg
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} // isBitcast
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def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
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(MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
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def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem,
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(outs), (ins i64mem:$dst, VR64:$src),
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@ -212,6 +212,13 @@ multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(store RC:$src, addr:$dst)], d>,
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Sched<[WriteFStore]>;
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def : InstAlias<"v"#OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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(!cast<Instruction>("V"#NAME#"rr_REV")
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VR128:$dst, VR128:$src1, VR128:$src2), 0>;
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def : InstAlias<OpcodeStr#".s\t{$src2, $dst|$dst, $src2}",
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(!cast<Instruction>(NAME#"rr_REV")
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VR128:$dst, VR128:$src2), 0>;
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}
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// Loading from memory automatically zeroing upper bits.
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@ -565,6 +572,24 @@ def : InstAlias<"vmovups\t{$src, $dst|$dst, $src}",
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def : InstAlias<"vmovupd\t{$src, $dst|$dst, $src}",
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(VMOVUPDYrr_REV VR256L:$dst, VR256H:$src), 0>;
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// Reversed version with ".s" suffix for GAS compatibility.
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def : InstAlias<"vmovaps.s\t{$src, $dst|$dst, $src}",
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(VMOVAPSrr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"vmovapd.s\t{$src, $dst|$dst, $src}",
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(VMOVAPDrr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"vmovups.s\t{$src, $dst|$dst, $src}",
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(VMOVUPSrr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"vmovupd.s\t{$src, $dst|$dst, $src}",
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(VMOVUPDrr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"vmovaps.s\t{$src, $dst|$dst, $src}",
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(VMOVAPSYrr_REV VR256:$dst, VR256:$src), 0>;
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def : InstAlias<"vmovapd.s\t{$src, $dst|$dst, $src}",
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(VMOVAPDYrr_REV VR256:$dst, VR256:$src), 0>;
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def : InstAlias<"vmovups.s\t{$src, $dst|$dst, $src}",
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(VMOVUPSYrr_REV VR256:$dst, VR256:$src), 0>;
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def : InstAlias<"vmovupd.s\t{$src, $dst|$dst, $src}",
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(VMOVUPDYrr_REV VR256:$dst, VR256:$src), 0>;
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let SchedRW = [SchedWriteFMoveLS.XMM.MR] in {
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def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movaps\t{$src, $dst|$dst, $src}",
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@ -597,6 +622,16 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
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FoldGenData<"MOVUPDrr">;
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}
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// Reversed version with ".s" suffix for GAS compatibility.
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def : InstAlias<"movaps.s\t{$src, $dst|$dst, $src}",
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(MOVAPSrr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"movapd.s\t{$src, $dst|$dst, $src}",
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(MOVAPDrr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"movups.s\t{$src, $dst|$dst, $src}",
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(MOVUPSrr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"movupd.s\t{$src, $dst|$dst, $src}",
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(MOVUPDrr_REV VR128:$dst, VR128:$src), 0>;
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let Predicates = [HasAVX, NoVLX] in {
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// 256-bit load/store need to use floating point load/store in case we don't
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// have AVX2. Execution domain fixing will convert to integer if AVX2 is
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@ -3350,6 +3385,22 @@ def : InstAlias<"vmovdqu\t{$src, $dst|$dst, $src}",
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def : InstAlias<"vmovdqu\t{$src, $dst|$dst, $src}",
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(VMOVDQUYrr_REV VR256L:$dst, VR256H:$src), 0>;
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// Reversed version with ".s" suffix for GAS compatibility.
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def : InstAlias<"vmovdqa.s\t{$src, $dst|$dst, $src}",
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(VMOVDQArr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"vmovdqa.s\t{$src, $dst|$dst, $src}",
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(VMOVDQAYrr_REV VR256:$dst, VR256:$src), 0>;
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def : InstAlias<"vmovdqu.s\t{$src, $dst|$dst, $src}",
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(VMOVDQUrr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"vmovdqu.s\t{$src, $dst|$dst, $src}",
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(VMOVDQUYrr_REV VR256:$dst, VR256:$src), 0>;
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// Reversed version with ".s" suffix for GAS compatibility.
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def : InstAlias<"movdqa.s\t{$src, $dst|$dst, $src}",
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(MOVDQArr_REV VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"movdqu.s\t{$src, $dst|$dst, $src}",
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(MOVDQUrr_REV VR128:$dst, VR128:$src), 0>;
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let Predicates = [HasAVX, NoVLX] in {
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// Additional patterns for other integer sizes.
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def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
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@ -4307,6 +4358,11 @@ def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
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def : InstAlias<"vmovq\t{$src, $dst|$dst, $src}",
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(VMOVPQI2QIrr VR128L:$dst, VR128H:$src), 0>;
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def : InstAlias<"vmovq.s\t{$src, $dst|$dst, $src}",
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(VMOVPQI2QIrr VR128:$dst, VR128:$src), 0>;
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def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
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(MOVPQI2QIrr VR128:$dst, VR128:$src), 0>;
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let Predicates = [UseAVX], AddedComplexity = 20 in {
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def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
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(VMOVQI2PQIrm addr:$src)>;
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@ -4691,54 +4691,6 @@
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// CHECK: encoding: [0x62,0x62,0x7d,0xc9,0x7b,0xc0]
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vpbroadcastw %eax, %zmm24 {%k1} {z}
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// CHECK: vpextrw $171, %xmm28, %eax
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// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0xab]
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vpextrw.s $0xab, %xmm28, %eax
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// CHECK: vpextrw $123, %xmm28, %eax
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// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0x7b]
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vpextrw.s $0x7b, %xmm28, %eax
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// CHECK: vpextrw $123, %xmm28, %r8d
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// CHECK: encoding: [0x62,0x43,0x7d,0x08,0x15,0xe0,0x7b]
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vpextrw.s $0x7b, %xmm28, %r8d
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// CHECK: vpextrw $171, %xmm28, %eax
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// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0xab]
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vpextrw.s $0xab, %xmm28, %eax
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// CHECK: vpextrw $123, %xmm28, %eax
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// CHECK: encoding: [0x62,0x63,0x7d,0x08,0x15,0xe0,0x7b]
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vpextrw.s $0x7b, %xmm28, %eax
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// CHECK: vpextrw $123, %xmm28, %r8d
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// CHECK: encoding: [0x62,0x43,0x7d,0x08,0x15,0xe0,0x7b]
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vpextrw.s $0x7b, %xmm28, %r8d
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// CHECK: vpextrw $171, %xmm20, %eax
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// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xe0,0xab]
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vpextrw.s $0xab, %xmm20, %eax
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// CHECK: vpextrw $123, %xmm20, %eax
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// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xe0,0x7b]
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vpextrw.s $0x7b, %xmm20, %eax
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// CHECK: vpextrw $123, %xmm20, %r8d
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// CHECK: encoding: [0x62,0xc3,0x7d,0x08,0x15,0xe0,0x7b]
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vpextrw.s $0x7b, %xmm20, %r8d
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// CHECK: vpextrw $171, %xmm19, %eax
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// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xd8,0xab]
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vpextrw.s $0xab, %xmm19, %eax
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// CHECK: vpextrw $123, %xmm19, %eax
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// CHECK: encoding: [0x62,0xe3,0x7d,0x08,0x15,0xd8,0x7b]
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vpextrw.s $0x7b, %xmm19, %eax
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// CHECK: vpextrw $123, %xmm19, %r8d
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// CHECK: encoding: [0x62,0xc3,0x7d,0x08,0x15,0xd8,0x7b]
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vpextrw.s $0x7b, %xmm19, %r8d
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// CHECK: vmovdqu16 %zmm19, %zmm22
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// CHECK: encoding: [0x62,0xa1,0xff,0x48,0x7f,0xde]
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vmovdqu16.s %zmm19, %zmm22
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@ -1635,6 +1635,126 @@ enclu
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// CHECK: encoding: [0x0f,0x01,0xc0]
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enclv
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// CHECK: movq %rax, %rbx
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// CHECK: encoding: [0x48,0x8b,0xd8]
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movq.s %rax, %rbx
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// CHECK: movq %rax, %rbx
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// CHECK: encoding: [0x48,0x8b,0xd8]
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mov.s %rax, %rbx
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// CHECK: movl %eax, %ebx
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// CHECK: encoding: [0x8b,0xd8]
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movl.s %eax, %ebx
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// CHECK: movl %eax, %ebx
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// CHECK: encoding: [0x8b,0xd8]
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mov.s %eax, %ebx
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// CHECK: movw %ax, %bx
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// CHECK: encoding: [0x66,0x8b,0xd8]
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movw.s %ax, %bx
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// CHECK: movw %ax, %bx
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// CHECK: encoding: [0x66,0x8b,0xd8]
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mov.s %ax, %bx
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// CHECK: movb %al, %bl
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// CHECK: encoding: [0x8a,0xd8]
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movb.s %al, %bl
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// CHECK: movb %al, %bl
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// CHECK: encoding: [0x8a,0xd8]
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mov.s %al, %bl
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// CHECK: movq %mm0, %mm1
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// CHECK: encoding: [0x0f,0x7f,0xc1]
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movq.s %mm0, %mm1
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// CHECK: movq %xmm0, %xmm1
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// CHECK: encoding: [0x66,0x0f,0xd6,0xc1]
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movq.s %xmm0, %xmm1
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// CHECK: movdqa %xmm0, %xmm1
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// CHECK: encoding: [0x66,0x0f,0x7f,0xc1]
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movdqa.s %xmm0, %xmm1
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// CHECK: movdqu %xmm0, %xmm1
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// CHECK: encoding: [0xf3,0x0f,0x7f,0xc1]
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movdqu.s %xmm0, %xmm1
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// CHECK: movaps %xmm0, %xmm1
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// CHECK: encoding: [0x0f,0x29,0xc1]
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movaps.s %xmm0, %xmm1
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// CHECK: movups %xmm0, %xmm1
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// CHECK: encoding: [0x0f,0x11,0xc1]
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movups.s %xmm0, %xmm1
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// CHECK: movapd %xmm0, %xmm1
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// CHECK: encoding: [0x66,0x0f,0x29,0xc1]
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movapd.s %xmm0, %xmm1
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// CHECK: movupd %xmm0, %xmm1
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// CHECK: encoding: [0x66,0x0f,0x11,0xc1]
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movupd.s %xmm0, %xmm1
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// CHECK: vmovq %xmm0, %xmm8
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// CHECK: encoding: [0xc4,0xc1,0x79,0xd6,0xc0]
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vmovq.s %xmm0, %xmm8
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// CHECK: vmovq %xmm8, %xmm0
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// CHECK: encoding: [0xc5,0x79,0xd6,0xc0]
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vmovq.s %xmm8, %xmm0
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// CHECK: vmovdqa %xmm0, %xmm8
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// CHECK: encoding: [0xc4,0xc1,0x79,0x7f,0xc0]
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vmovdqa.s %xmm0, %xmm8
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// CHECK: vmovdqa %xmm8, %xmm0
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// CHECK: encoding: [0xc5,0x79,0x7f,0xc0]
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vmovdqa.s %xmm8, %xmm0
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// CHECK: vmovdqu %xmm0, %xmm8
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// CHECK: encoding: [0xc4,0xc1,0x7a,0x7f,0xc0]
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vmovdqu.s %xmm0, %xmm8
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// CHECK: vmovdqu %xmm8, %xmm0
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// CHECK: encoding: [0xc5,0x7a,0x7f,0xc0]
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vmovdqu.s %xmm8, %xmm0
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// CHECK: vmovaps %xmm0, %xmm8
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// CHECK: encoding: [0xc4,0xc1,0x78,0x29,0xc0]
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vmovaps.s %xmm0, %xmm8
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// CHECK: vmovaps %xmm8, %xmm0
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// CHECK: encoding: [0xc5,0x78,0x29,0xc0]
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vmovaps.s %xmm8, %xmm0
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// CHECK: vmovups %xmm0, %xmm8
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// CHECK: encoding: [0xc4,0xc1,0x78,0x11,0xc0]
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vmovups.s %xmm0, %xmm8
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// CHECK: vmovups %xmm8, %xmm0
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// CHECK: encoding: [0xc5,0x78,0x11,0xc0]
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vmovups.s %xmm8, %xmm0
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// CHECK: vmovapd %xmm0, %xmm8
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// CHECK: encoding: [0xc4,0xc1,0x79,0x29,0xc0]
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vmovapd.s %xmm0, %xmm8
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// CHECK: vmovapd %xmm8, %xmm0
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// CHECK: encoding: [0xc5,0x79,0x29,0xc0]
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vmovapd.s %xmm8, %xmm0
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// CHECK: vmovupd %xmm0, %xmm8
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// CHECK: encoding: [0xc4,0xc1,0x79,0x11,0xc0]
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vmovupd.s %xmm0, %xmm8
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// CHECK: vmovupd %xmm8, %xmm0
|
||||
// CHECK: encoding: [0xc5,0x79,0x11,0xc0]
|
||||
vmovupd.s %xmm8, %xmm0
|
||||
|
||||
// __asm __volatile(
|
||||
// "pushf \n\t"
|
||||
// "popf \n\t"
|
||||
|
|
|
|||
Loading…
Reference in New Issue