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AMDGPU: Fix mishandling alignment when scalarizing vector loads/stores 

I don't think this was causing any real problems, so I'm not sure
how to test for this.

llvm-svn: 260646
This commit is contained in:
Matt Arsenault 2016-02-12 02:22:21 +00:00
parent 55d49cfe2d
commit 16f7bcb661
1 changed files with 5 additions and 2 deletions
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7
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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@ -1061,7 +1061,9 @@ SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
SmallVector<SDValue, 8> Chains;
SDLoc SL(Op);
unsigned BaseAlign = Load->getAlignment();
unsigned MemEltSize = MemEltVT.getStoreSize();
MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
for (unsigned i = 0; i < NumElts; ++i) {
@ -1073,7 +1075,7 @@ SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
Load->getChain(), Ptr,
SrcValue.getWithOffset(i * MemEltSize),
MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
Load->isInvariant(), Load->getAlignment());
Load->isInvariant(), MinAlign(BaseAlign, i * MemEltSize));
Loads.push_back(NewLoad.getValue(0));
Chains.push_back(NewLoad.getValue(1));
}
@ -1212,6 +1214,7 @@ SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
SmallVector<SDValue, 8> Chains;
unsigned BaseAlign = Store->getAlignment();
unsigned EltSize = MemEltVT.getStoreSize();
MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
@ -1226,7 +1229,7 @@ SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
SrcValue.getWithOffset(i * EltSize),
MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
Store->getAlignment());
MinAlign(BaseAlign, i * EltSize));
Chains.push_back(NewStore);
}