forked from OSchip/llvm-project
[AMDGPU] SIShrinkInstructions: sink code to where it's used. NFC.
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@ -771,10 +771,6 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
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const MachineOperand *SDst = TII->getNamedOperand(MI,
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const MachineOperand *SDst = TII->getNamedOperand(MI,
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AMDGPU::OpName::sdst);
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AMDGPU::OpName::sdst);
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// Check the carry-in operand for v_addc_u32_e64.
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const MachineOperand *Src2 = TII->getNamedOperand(MI,
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AMDGPU::OpName::src2);
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if (SDst) {
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if (SDst) {
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bool Next = false;
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bool Next = false;
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@ -786,6 +782,8 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
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// All of the instructions with carry outs also have an SGPR input in
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// All of the instructions with carry outs also have an SGPR input in
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// src2.
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// src2.
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const MachineOperand *Src2 = TII->getNamedOperand(MI,
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AMDGPU::OpName::src2);
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if (Src2 && Src2->getReg() != VCCReg) {
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if (Src2 && Src2->getReg() != VCCReg) {
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if (Src2->getReg().isVirtual())
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if (Src2->getReg().isVirtual())
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MRI.setRegAllocationHint(Src2->getReg(), 0, VCCReg);
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MRI.setRegAllocationHint(Src2->getReg(), 0, VCCReg);
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