forked from OSchip/llvm-project
[X86][X86 intrinsics]Folding cmp(sub(a,b),0) into cmp(a,b) optimization
This patch adds new optimization (Folding cmp(sub(a,b),0) into cmp(a,b)) to instCombineCall pass and was written specific for X86 CMP intrinsics. Differential Revision: https://reviews.llvm.org/D31398 llvm-svn: 300422
This commit is contained in:
Michael Zuckerman
parent
1bcc937b56
commit
16b20d2fc5
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@ -2337,6 +2337,37 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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return II;
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break;
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}
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case Intrinsic::x86_avx512_mask_cmp_pd_128:
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case Intrinsic::x86_avx512_mask_cmp_pd_256:
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case Intrinsic::x86_avx512_mask_cmp_pd_512:
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case Intrinsic::x86_avx512_mask_cmp_ps_128:
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case Intrinsic::x86_avx512_mask_cmp_ps_256:
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case Intrinsic::x86_avx512_mask_cmp_ps_512: {
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// Folding cmp(sub(a,b),0) -> cmp(a,b) and cmp(0,sub(a,b)) -> cmp(b,a)
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Value *Arg0 = II->getArgOperand(0);
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Value *Arg1 = II->getArgOperand(1);
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bool Arg0IsZero = match(Arg0, m_Zero());
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if (Arg0IsZero)
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std::swap(Arg0, Arg1);
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Value *A, *B;
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// This fold requires only the NINF(not +/- inf) since inf minus
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// inf is nan.
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// NSZ(No Signed Zeros) is not needed because zeros of any sign are
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// equal for both compares.
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// NNAN is not needed because nans compare the same for both compares.
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// The compare intrinsic uses the above assumptions and therefore
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// doesn't require additional flags.
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if ((match(Arg0, m_OneUse(m_FSub(m_Value(A), m_Value(B)))) &&
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match(Arg1, m_Zero()) &&
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cast<Instruction>(Arg0)->getFastMathFlags().noInfs())) {
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if (Arg0IsZero)
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std::swap(A, B);
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II->setArgOperand(0, A);
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II->setArgOperand(1, B);
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return II;
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}
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break;
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}
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case Intrinsic::x86_avx512_mask_add_ps_512:
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case Intrinsic::x86_avx512_mask_div_ps_512:
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@ -0,0 +1,181 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; The test checks the folding of cmp(sub(a,b),0) into cmp(a,b).
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define i8 @sub_compare_foldingPD128_safe(<2 x double> %a, <2 x double> %b){
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; CHECK-LABEL: @sub_compare_foldingPD128_safe(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SUB_SAFE:%.*]] = fsub <2 x double> [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> [[SUB_SAFE]], <2 x double> zeroinitializer, i32 5, i8 -1)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.safe = fsub <2 x double> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %sub.safe , <2 x double> zeroinitializer, i32 5, i8 -1)
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ret i8 %0
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}
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define i8 @sub_compare_foldingPD128(<2 x double> %a, <2 x double> %b){
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; CHECK-LABEL: @sub_compare_foldingPD128(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], i32 5, i8 -1)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i = fsub ninf <2 x double> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> %sub.i , <2 x double> zeroinitializer, i32 5, i8 -1)
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ret i8 %0
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}
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define i8 @sub_compare_foldingPD256(<4 x double> %a, <4 x double> %b){
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; CHECK-LABEL: @sub_compare_foldingPD256(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> [[A:%.*]], <4 x double> [[B:%.*]], i32 5, i8 -1)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i1 = fsub ninf <4 x double> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> %sub.i1, <4 x double> zeroinitializer, i32 5, i8 -1)
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ret i8 %0
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}
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define i8 @sub_compare_foldingPD512(<8 x double> %a, <8 x double> %b){
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; CHECK-LABEL: @sub_compare_foldingPD512(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 11, i8 -1, i32 4)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i2 = fsub ninf <8 x double> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> %sub.i2, <8 x double> zeroinitializer, i32 11, i8 -1, i32 4)
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ret i8 %0
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}
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define i8 @sub_compare_foldingPS128(<4 x float> %a, <4 x float> %b){
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; CHECK-LABEL: @sub_compare_foldingPS128(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], i32 12, i8 -1)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i3 = fsub ninf <4 x float> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> %sub.i3, <4 x float> zeroinitializer, i32 12, i8 -1)
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ret i8 %0
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}
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define i8 @sub_compare_foldingPS256(<8 x float> %a, <8 x float> %b){
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; CHECK-LABEL: @sub_compare_foldingPS256(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> [[A:%.*]], <8 x float> [[B:%.*]], i32 5, i8 -1)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i4 = fsub ninf <8 x float> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> %sub.i4, <8 x float> zeroinitializer, i32 5, i8 -1)
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ret i8 %0
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}
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define i16 @sub_compare_foldingPS512(<16 x float> %a, <16 x float> %b){
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; CHECK-LABEL: @sub_compare_foldingPS512(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 11, i16 -1, i32 4)
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; CHECK-NEXT: ret i16 [[TMP0]]
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;
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entry:
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%sub.i5 = fsub ninf <16 x float> %a, %b
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%0 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> %sub.i5, <16 x float> zeroinitializer, i32 11, i16 -1, i32 4)
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ret i16 %0
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}
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define i8 @sub_compare_folding_swapPD128(<2 x double> %a, <2 x double> %b){
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; CHECK-LABEL: @sub_compare_folding_swapPD128(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> [[B:%.*]], <2 x double> [[A:%.*]], i32 5, i8 -1)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i = fsub ninf <2 x double> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double> zeroinitializer, <2 x double> %sub.i, i32 5, i8 -1)
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ret i8 %0
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}
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define i8 @sub_compare_folding_swapPD256(<4 x double> %a, <4 x double> %b){
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; CHECK-LABEL: @sub_compare_folding_swapPD256(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> [[B:%.*]], <4 x double> [[A:%.*]], i32 5, i8 -1)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i = fsub ninf <4 x double> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double> zeroinitializer, <4 x double> %sub.i, i32 5, i8 -1)
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ret i8 %0
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}
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define i8 @sub_compare_folding_swapPD512(<8 x double> %a, <8 x double> %b){
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; CHECK-LABEL: @sub_compare_folding_swapPD512(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> [[B:%.*]], <8 x double> [[A:%.*]], i32 11, i8 -1, i32 4)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i = fsub ninf <8 x double> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double> zeroinitializer, <8 x double> %sub.i, i32 11, i8 -1, i32 4)
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ret i8 %0
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}
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define i8 @sub_compare_folding_swapPS128(<4 x float> %a, <4 x float> %b){
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; CHECK-LABEL: @sub_compare_folding_swapPS128(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> [[B:%.*]], <4 x float> [[A:%.*]], i32 12, i8 -1)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i = fsub ninf <4 x float> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float> zeroinitializer, <4 x float> %sub.i, i32 12, i8 -1)
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ret i8 %0
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}
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define i8 @sub_compare_folding_swapPS256(<8 x float> %a, <8 x float> %b){
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; CHECK-LABEL: @sub_compare_folding_swapPS256(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> [[B:%.*]], <8 x float> [[A:%.*]], i32 5, i8 -1)
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; CHECK-NEXT: ret i8 [[TMP0]]
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;
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entry:
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%sub.i = fsub ninf <8 x float> %a, %b
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%0 = tail call i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float> zeroinitializer, <8 x float> %sub.i, i32 5, i8 -1)
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ret i8 %0
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}
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define i16 @sub_compare_folding_swapPS512(<16 x float> %a, <16 x float> %b){
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; CHECK-LABEL: @sub_compare_folding_swapPS512(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> [[B:%.*]], <16 x float> [[A:%.*]], i32 11, i16 -1, i32 4)
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; CHECK-NEXT: ret i16 [[TMP0]]
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;
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entry:
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%sub.i = fsub ninf <16 x float> %a, %b
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%0 = tail call i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float> zeroinitializer, <16 x float> %sub.i, i32 11, i16 -1, i32 4)
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ret i16 %0
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}
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declare i8 @llvm.x86.avx512.mask.cmp.pd.128(<2 x double>, <2 x double>, i32, i8)
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declare i8 @llvm.x86.avx512.mask.cmp.pd.256(<4 x double>, <4 x double>, i32, i8)
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declare i8 @llvm.x86.avx512.mask.cmp.pd.512(<8 x double>, <8 x double>, i32, i8, i32)
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declare i8 @llvm.x86.avx512.mask.cmp.ps.128(<4 x float>, <4 x float>, i32, i8)
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declare i8 @llvm.x86.avx512.mask.cmp.ps.256(<8 x float>, <8 x float>, i32, i8)
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declare i16 @llvm.x86.avx512.mask.cmp.ps.512(<16 x float>, <16 x float>, i32, i16, i32)
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