forked from OSchip/llvm-project
parent
3c9f5f45f6
commit
16af2d5aa8
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@ -55,6 +55,7 @@ namespace {
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// fixed X86 code for each instruction.
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//
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void visitReturnInst(ReturnInst &RI);
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void visitBranchInst(BranchInst &BI);
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void visitAdd(BinaryOperator &B);
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void visitShiftInst(ShiftInst &I);
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@ -162,6 +163,14 @@ void ISel::visitReturnInst(ReturnInst &I) {
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BuildMI(BB, X86::RET, 0);
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}
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void ISel::visitBranchInst(BranchInst &BI) {
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if (BI.isConditional()) // Only handles unconditional branches so far...
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visitInstruction(BI);
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BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
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}
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/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
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/// for constant immediate shift values, and for constant immediate
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/// shift values equal to 1. Even the general case is sort of special,
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@ -33,8 +33,9 @@ I(PHI , "phi", 0, 0)
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// The second instruction must always be the noop instruction: (FIXME, not yet)
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I(NOOP , "nop", 0, X86II::Void) // nop 90
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// Miscellaneous instructions
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// Flow control instructions
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I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB
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I(JMP , "jmp", M_BRANCH_FLAG, X86II::Void) // jmp foo EB|E9 cb|w
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// Move instructions
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I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r
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