forked from OSchip/llvm-project
parent
1d9ba08543
commit
167b302075
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@ -986,11 +986,11 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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static bool matchRegisterNameHelper(bool IsRV32E, Register &RegNo,
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StringRef Name) {
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RegNo = MatchRegisterName(Name);
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if (RegNo == NoRegister)
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if (RegNo == RISCV::NoRegister)
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RegNo = MatchRegisterAltName(Name);
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if (IsRV32E && RegNo >= RISCV::X16 && RegNo <= RISCV::X31)
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RegNo = NoRegister;
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return RegNo == NoRegister;
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RegNo = RISCV::NoRegister;
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return RegNo == RISCV::NoRegister;
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}
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bool RISCVAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
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@ -1036,7 +1036,7 @@ OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands,
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Register RegNo;
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matchRegisterNameHelper(isRV32E(), RegNo, Name);
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if (RegNo == NoRegister) {
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if (RegNo == RISCV::NoRegister) {
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if (HadParens)
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getLexer().UnLex(LParen);
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return MatchOperand_NoMatch;
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