forked from OSchip/llvm-project
Simplify SelectionDAG::getNode so that a big switch stmt is not #ifndef
NDEBUG. This is in response to a really nasty bug I introduced that Dale tracked down, hopefully this won't happen in the future. Many thanks Dale. llvm-svn: 46254
This commit is contained in:
Chris Lattner
parent
f52da44530
commit
1671361c5c
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@ -1859,15 +1859,34 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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SDOperand N1, SDOperand N2) {
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#ifndef NDEBUG
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
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switch (Opcode) {
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default: break;
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case ISD::TokenFactor:
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assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
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N2.getValueType() == MVT::Other && "Invalid token factor!");
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// Fold trivial token factors.
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if (N1.getOpcode() == ISD::EntryToken) return N2;
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if (N2.getOpcode() == ISD::EntryToken) return N1;
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break;
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case ISD::AND:
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assert(MVT::isInteger(VT) && N1.getValueType() == N2.getValueType() &&
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N1.getValueType() == VT && "Binary operator types must match!");
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// (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's
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// worth handling here.
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if (N2C && N2C->getValue() == 0)
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return N2;
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break;
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case ISD::OR:
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case ISD::XOR:
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assert(MVT::isInteger(VT) && N1.getValueType() == N2.getValueType() &&
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N1.getValueType() == VT && "Binary operator types must match!");
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// (X ^| 0) -> X. This commonly occurs when legalizing i64 values, so it's
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// worth handling here.
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if (N2C && N2C->getValue() == 0)
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return N1;
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break;
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case ISD::UDIV:
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case ISD::UREM:
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case ISD::MULHU:
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@ -1879,8 +1898,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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case ISD::MUL:
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case ISD::SDIV:
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case ISD::SREM:
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assert(MVT::isInteger(N1.getValueType()) && "Should use F* for FP ops");
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// fall through.
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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@ -1912,6 +1929,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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"Cannot FP_ROUND_INREG integer types");
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assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) &&
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"Not rounding down!");
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if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding.
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break;
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}
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case ISD::FP_ROUND:
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@ -1919,9 +1937,18 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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MVT::isFloatingPoint(N1.getValueType()) &&
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MVT::getSizeInBits(VT) <= MVT::getSizeInBits(N1.getValueType()) &&
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isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
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if (N1.getValueType() == VT) return N1; // noop conversion.
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break;
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case ISD::AssertSext:
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case ISD::AssertZext:
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case ISD::AssertZext: {
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MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT();
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assert(VT == N1.getValueType() && "Not an inreg extend!");
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assert(MVT::isInteger(VT) && MVT::isInteger(EVT) &&
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"Cannot *_EXTEND_INREG FP types");
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assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) &&
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"Not extending!");
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break;
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}
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case ISD::SIGN_EXTEND_INREG: {
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MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT();
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assert(VT == N1.getValueType() && "Not an inreg extend!");
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@ -1929,23 +1956,64 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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"Cannot *_EXTEND_INREG FP types");
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assert(MVT::getSizeInBits(EVT) <= MVT::getSizeInBits(VT) &&
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"Not extending!");
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}
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if (EVT == VT) return N1; // Not actually extending
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default: break;
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}
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#endif
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
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if (N1C) {
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if (Opcode == ISD::SIGN_EXTEND_INREG) {
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if (N1C) {
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int64_t Val = N1C->getValue();
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unsigned FromBits = MVT::getSizeInBits(cast<VTSDNode>(N2)->getVT());
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Val <<= 64-FromBits;
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Val >>= 64-FromBits;
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return getConstant(Val, VT);
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}
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break;
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}
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case ISD::EXTRACT_VECTOR_ELT:
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assert(N2C && "Bad EXTRACT_VECTOR_ELT!");
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// EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
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// expanding copies of large vectors from registers.
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if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
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N1.getNumOperands() > 0) {
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unsigned Factor =
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MVT::getVectorNumElements(N1.getOperand(0).getValueType());
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return getNode(ISD::EXTRACT_VECTOR_ELT, VT,
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N1.getOperand(N2C->getValue() / Factor),
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getConstant(N2C->getValue() % Factor, N2.getValueType()));
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}
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// EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is
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// expanding large vector constants.
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if (N1.getOpcode() == ISD::BUILD_VECTOR)
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return N1.getOperand(N2C->getValue());
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// EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
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// operations are lowered to scalars.
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if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT)
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if (ConstantSDNode *IEC = dyn_cast<ConstantSDNode>(N1.getOperand(2))) {
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if (IEC == N2C)
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return N1.getOperand(1);
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else
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return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2);
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}
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break;
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case ISD::EXTRACT_ELEMENT:
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assert(N2C && (unsigned)N2C->getValue() < 2 && "Bad EXTRACT_ELEMENT!");
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// EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
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// 64-bit integers into 32-bit parts. Instead of building the extract of
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// the BUILD_PAIR, only to have legalize rip it apart, just do it now.
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if (N1.getOpcode() == ISD::BUILD_PAIR)
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return N1.getOperand(N2C->getValue());
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// EXTRACT_ELEMENT of a constant int is also very common.
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
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unsigned Shift = MVT::getSizeInBits(VT) * N2C->getValue();
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return getConstant(C->getValue() >> Shift, VT);
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}
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break;
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}
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if (N1C) {
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if (N2C) {
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uint64_t C1 = N1C->getValue(), C2 = N2C->getValue();
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switch (Opcode) {
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@ -1988,16 +2056,21 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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}
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}
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// Constant fold FP operations.
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ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
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ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val);
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if (N1CFP) {
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if (N2CFP && VT!=MVT::ppcf128) {
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if (!N2CFP && isCommutativeBinOp(Opcode)) {
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// Cannonicalize constant to RHS if commutative
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std::swap(N1CFP, N2CFP);
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std::swap(N1, N2);
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} else if (N2CFP && VT != MVT::ppcf128) {
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APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
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APFloat::opStatus s;
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switch (Opcode) {
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case ISD::FADD:
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s = V1.add(V2, APFloat::rmNearestTiesToEven);
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if (s!=APFloat::opInvalidOp)
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if (s != APFloat::opInvalidOp)
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return getConstantFP(V1, VT);
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break;
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case ISD::FSUB:
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@ -2025,11 +2098,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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return getConstantFP(V1, VT);
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default: break;
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}
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} else { // Cannonicalize constant to RHS if commutative
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if (isCommutativeBinOp(Opcode)) {
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std::swap(N1CFP, N2CFP);
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std::swap(N1, N2);
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}
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}
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}
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@ -2100,105 +2168,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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}
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}
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// Fold operations.
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switch (Opcode) {
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case ISD::TokenFactor:
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// Fold trivial token factors.
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if (N1.getOpcode() == ISD::EntryToken) return N2;
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if (N2.getOpcode() == ISD::EntryToken) return N1;
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break;
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case ISD::AND:
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// (X & 0) -> 0. This commonly occurs when legalizing i64 values, so it's
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// worth handling here.
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if (N2C && N2C->getValue() == 0)
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return N2;
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break;
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case ISD::OR:
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case ISD::XOR:
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// (X ^| 0) -> X. This commonly occurs when legalizing i64 values, so it's
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// worth handling here.
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if (N2C && N2C->getValue() == 0)
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return N1;
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break;
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case ISD::FP_ROUND:
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if (N1.getValueType() == VT) return N1; // noop conversion.
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break;
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case ISD::FP_ROUND_INREG:
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if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding.
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break;
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case ISD::SIGN_EXTEND_INREG: {
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MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT();
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if (EVT == VT) return N1; // Not actually extending
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break;
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}
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case ISD::EXTRACT_VECTOR_ELT:
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assert(N2C && "Bad EXTRACT_VECTOR_ELT!");
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// EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
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// expanding copies of large vectors from registers.
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if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
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N1.getNumOperands() > 0) {
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unsigned Factor =
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MVT::getVectorNumElements(N1.getOperand(0).getValueType());
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return getNode(ISD::EXTRACT_VECTOR_ELT, VT,
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N1.getOperand(N2C->getValue() / Factor),
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getConstant(N2C->getValue() % Factor, N2.getValueType()));
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}
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// EXTRACT_VECTOR_ELT of BUILD_VECTOR is often formed while lowering is
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// expanding large vector constants.
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if (N1.getOpcode() == ISD::BUILD_VECTOR)
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return N1.getOperand(N2C->getValue());
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// EXTRACT_VECTOR_ELT of INSERT_VECTOR_ELT is often formed when vector
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// operations are lowered to scalars.
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if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT)
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if (ConstantSDNode *IEC = dyn_cast<ConstantSDNode>(N1.getOperand(2))) {
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if (IEC == N2C)
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return N1.getOperand(1);
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else
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return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2);
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}
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break;
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case ISD::EXTRACT_ELEMENT:
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assert(N2C && (unsigned)N2C->getValue() < 2 && "Bad EXTRACT_ELEMENT!");
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// EXTRACT_ELEMENT of BUILD_PAIR is often formed while legalize is expanding
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// 64-bit integers into 32-bit parts. Instead of building the extract of
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// the BUILD_PAIR, only to have legalize rip it apart, just do it now.
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if (N1.getOpcode() == ISD::BUILD_PAIR)
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return N1.getOperand(N2C->getValue());
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// EXTRACT_ELEMENT of a constant int is also very common.
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
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unsigned Shift = MVT::getSizeInBits(VT) * N2C->getValue();
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return getConstant(C->getValue() >> Shift, VT);
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}
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break;
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// FIXME: figure out how to safely handle things like
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// int foo(int x) { return 1 << (x & 255); }
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// int bar() { return foo(256); }
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#if 0
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case ISD::SHL:
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case ISD::SRL:
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case ISD::SRA:
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if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG &&
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cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1)
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return getNode(Opcode, VT, N1, N2.getOperand(0));
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else if (N2.getOpcode() == ISD::AND)
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) {
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// If the and is only masking out bits that cannot effect the shift,
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// eliminate the and.
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unsigned NumBits = MVT::getSizeInBits(VT);
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if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
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return getNode(Opcode, VT, N1, N2.getOperand(0));
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}
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break;
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#endif
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}
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// Memoize this node if possible.
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SDNode *N;
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SDVTList VTs = getVTList(VT);
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