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[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead. 

This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch.

llvm-svn: 297596
This commit is contained in:
Craig Topper 2017-03-13 00:36:49 +00:00
parent 9fc4135cc2
commit 166085f0f2
2 changed files with 7 additions and 6 deletions
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8
llvm/test/CodeGen/X86/evex-to-vex-compress.mir
View File

@ -2172,7 +2172,7 @@ body: |
%rdi = VCVTSS2SI64Zrr %xmm0
; CHECK: %edi = VCVTSS2SIrr %xmm0
%edi = VCVTSS2SIZrr %xmm0
; CHECK: %rdi = VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0
; CHECK: %rdi = Int_VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0
%rdi = VCVTTSD2SI64Zrm %rdi, %xmm0, 1, _, 0
; CHECK: %rdi = Int_VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0
%rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm0, 1, _, 0
@ -2180,7 +2180,7 @@ body: |
%rdi = VCVTTSD2SI64Zrr %xmm0
; CHECK: %rdi = Int_VCVTTSD2SI64rr %xmm0
%rdi = VCVTTSD2SI64Zrr_Int %xmm0
; CHECK: %edi = VCVTTSD2SIrm %rdi, %xmm0, 1, _, 0
; CHECK: %edi = Int_VCVTTSD2SIrm %rdi, %xmm0, 1, _, 0
%edi = VCVTTSD2SIZrm %rdi, %xmm0, 1, _, 0
; CHECK: %edi = Int_VCVTTSD2SIrm %rdi, %xmm0, 1, _, 0
%edi = VCVTTSD2SIZrm_Int %rdi, %xmm0, 1, _, 0
@ -2188,7 +2188,7 @@ body: |
%edi = VCVTTSD2SIZrr %xmm0
; CHECK: %edi = Int_VCVTTSD2SIrr %xmm0
%edi = VCVTTSD2SIZrr_Int %xmm0
; CHECK: %rdi = VCVTTSS2SI64rm %rdi, %xmm0, 1, _, 0
; CHECK: %rdi = Int_VCVTTSS2SI64rm %rdi, %xmm0, 1, _, 0
%rdi = VCVTTSS2SI64Zrm %rdi, %xmm0, 1, _, 0
; CHECK: %rdi = Int_VCVTTSS2SI64rm %rdi, %xmm0, 1, _, 0
%rdi = VCVTTSS2SI64Zrm_Int %rdi, %xmm0, 1, _, 0
@ -2196,7 +2196,7 @@ body: |
%rdi = VCVTTSS2SI64Zrr %xmm0
; CHECK: %rdi = Int_VCVTTSS2SI64rr %xmm0
%rdi = VCVTTSS2SI64Zrr_Int %xmm0
; CHECK: %edi = VCVTTSS2SIrm %rdi, %xmm0, 1, _, 0
; CHECK: %edi = Int_VCVTTSS2SIrm %rdi, %xmm0, 1, _, 0
%edi = VCVTTSS2SIZrm %rdi, %xmm0, 1, _, 0
; CHECK: %edi = Int_VCVTTSS2SIrm %rdi, %xmm0, 1, _, 0
%edi = VCVTTSS2SIZrm_Int %rdi, %xmm0, 1, _, 0

5
llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
View File

@ -72,7 +72,8 @@ private:
"VPSRAQ",
"VDBPSADBW",
"VRNDSCALE",
"VSCALEFPS"
"VSCALEFPS",
"VSCALEFSS",
};
bool inExceptionList(const CodeGenInstruction *Inst) {
@ -242,7 +243,7 @@ public:
if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
return false;
} else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
return false;
continue;
} else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type"))
return false;