From 166085f0f267c8af3e448465066bc16195e374e4 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 13 Mar 2017 00:36:49 +0000 Subject: [PATCH] [AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead. This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch. llvm-svn: 297596 --- llvm/test/CodeGen/X86/evex-to-vex-compress.mir | 8 ++++---- llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp | 5 +++-- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir index 138cd540ccee..8b28ea1d03f9 100755 --- a/llvm/test/CodeGen/X86/evex-to-vex-compress.mir +++ b/llvm/test/CodeGen/X86/evex-to-vex-compress.mir @@ -2172,7 +2172,7 @@ body: | %rdi = VCVTSS2SI64Zrr %xmm0 ; CHECK: %edi = VCVTSS2SIrr %xmm0 %edi = VCVTSS2SIZrr %xmm0 - ; CHECK: %rdi = VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0 + ; CHECK: %rdi = Int_VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0 %rdi = VCVTTSD2SI64Zrm %rdi, %xmm0, 1, _, 0 ; CHECK: %rdi = Int_VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0 %rdi = VCVTTSD2SI64Zrm_Int %rdi, %xmm0, 1, _, 0 @@ -2180,7 +2180,7 @@ body: | %rdi = VCVTTSD2SI64Zrr %xmm0 ; CHECK: %rdi = Int_VCVTTSD2SI64rr %xmm0 %rdi = VCVTTSD2SI64Zrr_Int %xmm0 - ; CHECK: %edi = VCVTTSD2SIrm %rdi, %xmm0, 1, _, 0 + ; CHECK: %edi = Int_VCVTTSD2SIrm %rdi, %xmm0, 1, _, 0 %edi = VCVTTSD2SIZrm %rdi, %xmm0, 1, _, 0 ; CHECK: %edi = Int_VCVTTSD2SIrm %rdi, %xmm0, 1, _, 0 %edi = VCVTTSD2SIZrm_Int %rdi, %xmm0, 1, _, 0 @@ -2188,7 +2188,7 @@ body: | %edi = VCVTTSD2SIZrr %xmm0 ; CHECK: %edi = Int_VCVTTSD2SIrr %xmm0 %edi = VCVTTSD2SIZrr_Int %xmm0 - ; CHECK: %rdi = VCVTTSS2SI64rm %rdi, %xmm0, 1, _, 0 + ; CHECK: %rdi = Int_VCVTTSS2SI64rm %rdi, %xmm0, 1, _, 0 %rdi = VCVTTSS2SI64Zrm %rdi, %xmm0, 1, _, 0 ; CHECK: %rdi = Int_VCVTTSS2SI64rm %rdi, %xmm0, 1, _, 0 %rdi = VCVTTSS2SI64Zrm_Int %rdi, %xmm0, 1, _, 0 @@ -2196,7 +2196,7 @@ body: | %rdi = VCVTTSS2SI64Zrr %xmm0 ; CHECK: %rdi = Int_VCVTTSS2SI64rr %xmm0 %rdi = VCVTTSS2SI64Zrr_Int %xmm0 - ; CHECK: %edi = VCVTTSS2SIrm %rdi, %xmm0, 1, _, 0 + ; CHECK: %edi = Int_VCVTTSS2SIrm %rdi, %xmm0, 1, _, 0 %edi = VCVTTSS2SIZrm %rdi, %xmm0, 1, _, 0 ; CHECK: %edi = Int_VCVTTSS2SIrm %rdi, %xmm0, 1, _, 0 %edi = VCVTTSS2SIZrm_Int %rdi, %xmm0, 1, _, 0 diff --git a/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp b/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp index 24f84aec6ca6..142a969d340b 100644 --- a/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp @@ -72,7 +72,8 @@ private: "VPSRAQ", "VDBPSADBW", "VRNDSCALE", - "VSCALEFPS" + "VSCALEFPS", + "VSCALEFSS", }; bool inExceptionList(const CodeGenInstruction *Inst) { @@ -242,7 +243,7 @@ public: if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2)) return false; } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) { - return false; + continue; } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) { if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type")) return false;