forked from OSchip/llvm-project
parent
6feef56d1b
commit
165846b031
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@ -336,6 +336,14 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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&ARM::ValueMappings[ARM::GPR3OpsIdx]});
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break;
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}
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case G_FCONSTANT: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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OperandsMapping = getOperandsMapping(
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{Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx]
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: &ARM::ValueMappings[ARM::SPR3OpsIdx],
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nullptr});
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break;
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}
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case G_CONSTANT:
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case G_FRAME_INDEX:
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case G_GLOBAL_VALUE:
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@ -71,6 +71,9 @@
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define void @test_fpext_s32_to_s64() #0 { ret void }
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define void @test_fptrunc_s64_to_s32() #0 { ret void }
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define void @test_fpconst_s32() #0 { ret void }
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define void @test_fpconst_s64() #0 { ret void }
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define void @test_fptosi_s32() #0 { ret void }
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define void @test_fptosi_s64() #0 { ret void }
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define void @test_fptoui_s32() #0 { ret void }
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@ -1287,6 +1290,42 @@ body: |
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BX_RET 14, $noreg, implicit $s0
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...
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---
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name: test_fpconst_s32
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# CHECK-LABEL: name: test_fpconst_s32
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: fprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0:
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liveins:
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%0(s32) = G_FCONSTANT float -1.25
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$s0 = COPY %0(s32)
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BX_RET 14, $noreg, implicit $s0
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...
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---
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name: test_fpconst_s64
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# CHECK-LABEL: name: test_fpconst_s64
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legalized: true
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regBankSelected: false
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selected: false
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# CHECK: registers:
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# CHECK: - { id: 0, class: fprb, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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body: |
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bb.0:
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liveins:
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%0(s64) = G_FCONSTANT double -2.4
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$d0 = COPY %0(s64)
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BX_RET 14, $noreg, implicit $d0
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...
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---
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name: test_fptosi_s32
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# CHECK-LABEL: name: test_fptosi_s32
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legalized: true
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