maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[RISCV] Share RVInstIShift and RVInstIShiftW instruction format classes with the B extension. 

This generalizes RVInstIShift/RVInstIShiftW to take the upper
5 or 7 bits of the immediate as an input instead of only bit 30. Then
we can share them.

For RVInstIShift I left a hardcoded 0 at bit 26 where RV128 gets
a 7th bit for the shift amount.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D100424
This commit is contained in:
Craig Topper 2021-04-15 11:08:26 -07:00
parent e0c2125d1d
commit 1656df13da
3 changed files with 31 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
llvm/lib/Target/RISCV/RISCVInstrFormats.td
View File

@ -302,16 +302,15 @@ class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
let Opcode = opcode.Value;
}
class RVInstIShift<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
bits<6> shamt;
bits<5> rs1;
bits<5> rd;
let Inst{31} = 0;
let Inst{30} = arithshift;
let Inst{29-26} = 0;
let Inst{31-27} = imm11_7;
let Inst{26} = 0;
let Inst{25-20} = shamt;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
@ -319,16 +318,14 @@ class RVInstIShift<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
let Opcode = opcode.Value;
}
class RVInstIShiftW<bit arithshift, bits<3> funct3, RISCVOpcode opcode,
class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
bits<5> shamt;
bits<5> rs1;
bits<5> rd;
let Inst{31} = 0;
let Inst{30} = arithshift;
let Inst{29-25} = 0;
let Inst{31-25} = imm11_5;
let Inst{24-20} = shamt;
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;

20
llvm/lib/Target/RISCV/RISCVInstrInfo.td
View File

@ -384,8 +384,8 @@ class ALU_ri<bits<3> funct3, string opcodestr>
Sched<[WriteIALU, ReadIALU]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class Shift_ri<bit arithshift, bits<3> funct3, string opcodestr>
: RVInstIShift<arithshift, funct3, OPC_OP_IMM, (outs GPR:$rd),
class Shift_ri<bits<5> imm11_7, bits<3> funct3, string opcodestr>
: RVInstIShift<imm11_7, funct3, OPC_OP_IMM, (outs GPR:$rd),
(ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
"$rd, $rs1, $shamt">,
Sched<[WriteShiftImm, ReadShiftImm]>;
@ -409,8 +409,8 @@ class CSR_ii<bits<3> funct3, string opcodestr>
opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class ShiftW_ri<bit arithshift, bits<3> funct3, string opcodestr>
: RVInstIShiftW<arithshift, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
class ShiftW_ri<bits<7> imm11_5, bits<3> funct3, string opcodestr>
: RVInstIShiftW<imm11_5, funct3, OPC_OP_IMM_32, (outs GPR:$rd),
(ins GPR:$rs1, uimm5:$shamt), opcodestr,
"$rd, $rs1, $shamt">,
Sched<[WriteShiftImm32, ReadShiftImm32]>;
@ -480,9 +480,9 @@ def ORI : ALU_ri<0b110, "ori">;
def ANDI : ALU_ri<0b111, "andi">;
def SLLI : Shift_ri<0, 0b001, "slli">;
def SRLI : Shift_ri<0, 0b101, "srli">;
def SRAI : Shift_ri<1, 0b101, "srai">;
def SLLI : Shift_ri<0b00000, 0b001, "slli">;
def SRLI : Shift_ri<0b00000, 0b101, "srli">;
def SRAI : Shift_ri<0b01000, 0b101, "srai">;
def ADD : ALU_rr<0b0000000, 0b000, "add">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def SUB : ALU_rr<0b0100000, 0b000, "sub">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
@ -564,9 +564,9 @@ def ADDIW : RVInstI<0b000, OPC_OP_IMM_32, (outs GPR:$rd),
"addiw", "$rd, $rs1, $imm12">,
Sched<[WriteIALU32, ReadIALU32]>;
def SLLIW : ShiftW_ri<0, 0b001, "slliw">;
def SRLIW : ShiftW_ri<0, 0b101, "srliw">;
def SRAIW : ShiftW_ri<1, 0b101, "sraiw">;
def SLLIW : ShiftW_ri<0b0000000, 0b001, "slliw">;
def SRLIW : ShiftW_ri<0b0000000, 0b101, "srliw">;
def SRAIW : ShiftW_ri<0b0100000, 0b101, "sraiw">;
def ADDW : ALUW_rr<0b0000000, 0b000, "addw">,
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;

46
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
View File

@ -92,46 +92,30 @@ class RVBUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3,
RISCVOpcode opcode, string opcodestr>
: RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
opcodestr, "$rd, $rs1"> {
let Inst{24-20} = funct5;
let rs2 = funct5;
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVBShift_ri<bits<5> funct5, bits<3> funct3, RISCVOpcode opcode,
class RVBShift_ri<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
string opcodestr>
: RVInstI<funct3, opcode, (outs GPR:$rd),
: RVInstIShift<imm11_7, funct3, opcode, (outs GPR:$rd),
(ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
"$rd, $rs1, $shamt"> {
bits<6> shamt;
let Inst{31-27} = funct5;
// NOTE: the bit op(26)=1 is used to select funnel shifts. All other
// shifts operations and operations that live in the encoding space
// of the shifts (single bit operations, grev, gorc) use op(26) = 0
let Inst{26} = 0;
let Inst{25-20} = shamt;
}
"$rd, $rs1, $shamt">;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVBShiftW_ri<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,
class RVBShiftW_ri<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
string opcodestr>
: RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$shamt),
opcodestr, "$rd, $rs1, $shamt"> {
bits<5> shamt;
let Inst{31-25} = funct7;
let Inst{24-20} = shamt;
}
: RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
(ins GPR:$rs1, uimm5:$shamt), opcodestr,
"$rd, $rs1, $shamt">;
// Using RVInstIShiftW since it allocates 5 bits instead of 6 to shamt.
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVBShfl_ri<bits<6> funct6, bits<3> funct3, RISCVOpcode opcode,
class RVBShfl_ri<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
string opcodestr>
: RVInstI<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, shfl_uimm:$shamt),
opcodestr, "$rd, $rs1, $shamt"> {
bits<6> shamt;
let Inst{31-26} = funct6;
let Inst{25-20} = shamt;
}
: RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
(ins GPR:$rs1, shfl_uimm:$shamt), opcodestr,
"$rd, $rs1, $shamt">;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVBTernaryR<bits<2> funct2, bits<3> funct3_b, RISCVOpcode opcode,
@ -338,8 +322,8 @@ let Predicates = [HasStdExtZbf] in
def BFP : ALU_rr<0b0100100, 0b111, "bfp">, Sched<[]>;
let Predicates = [HasStdExtZbp] in {
def SHFLI : RVBShfl_ri<0b000010, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
def UNSHFLI : RVBShfl_ri<0b000010, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
def SHFLI : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
} // Predicates = [HasStdExtZbp]
let Predicates = [HasStdExtZba, IsRV64] in {