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[AArch64] enhance test to show FMF loss; NFC 

llvm-svn: 332301
This commit is contained in:
Sanjay Patel 2018-05-14 21:53:21 +00:00
parent 434019a617
commit 165587b424
1 changed files with 2 additions and 1 deletions
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3
llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
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@ -9,6 +9,7 @@
; CHECK-NEXT: Analyzing result type: v4f64 ; CHECK-NEXT: Analyzing result type: v4f64
; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR ; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR
; FIXME: We dropped the 'reassoc' flag.
; CHECK: Legalizing node: [[VTWO:t.*]]: v2f64 = BUILD_VECTOR ; CHECK: Legalizing node: [[VTWO:t.*]]: v2f64 = BUILD_VECTOR
; CHECK: Legally typed node: [[VTWO]]: v2f64 = BUILD_VECTOR ; CHECK: Legally typed node: [[VTWO]]: v2f64 = BUILD_VECTOR
; CHECK: Legalizing node: t26: v2f64 = fmaxnum nnan [[VTWO]], [[VTWO]] ; CHECK: Legalizing node: t26: v2f64 = fmaxnum nnan [[VTWO]], [[VTWO]]
@ -24,7 +25,7 @@ entry:
%1 = insertelement <4 x double> %0, double 1.0, i32 1 %1 = insertelement <4 x double> %0, double 1.0, i32 1
%2 = insertelement <4 x double> %1, double 1.0, i32 2 %2 = insertelement <4 x double> %1, double 1.0, i32 2
%3 = insertelement <4 x double> %2, double 1.0, i32 3 %3 = insertelement <4 x double> %2, double 1.0, i32 3
%4 = call nnan double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double> %3) %4 = call nnan reassoc double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double> %3)
ret double %4 ret double %4
} }