diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 0d90fc074879..6c5d386f029c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3343,7 +3343,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
 
   // Do not generate loads of non-round integer types since these can
   // be expensive (and would be wrong if the type is not byte sized).
-  if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() &&
+  if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
       cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
       // Do not change the width of a volatile load.
       !cast<LoadSDNode>(N0)->isVolatile()) {
diff --git a/llvm/test/CodeGen/X86/pr3216.ll b/llvm/test/CodeGen/X86/pr3216.ll
new file mode 100644
index 000000000000..fdc814ef3376
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr3216.ll
@@ -0,0 +1,14 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep {sar.	\$5}
+
+@foo = global i8 127
+
+define i32 @main() nounwind {
+entry:
+        %tmp = load i8* @foo
+        %bf.lo = lshr i8 %tmp, 5
+        %bf.lo.cleared = and i8 %bf.lo, 7
+        %0 = shl i8 %bf.lo.cleared, 5
+        %bf.val.sext = ashr i8 %0, 5
+        %conv = sext i8 %bf.val.sext to i32
+        ret i32 %conv
+}