forked from OSchip/llvm-project
Fix PR7174, a couple o Mips fixes:
- Fix a typo for PIC check during jmp table lowering - Also fix the "first jump table basic block is not considered only reachable by fall through" problem, use this ad-hoc solution until I come up with something better. Patch by stetorvs@gmail.com llvm-svn: 108820
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@ -18,6 +18,8 @@
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#include "MipsInstrInfo.h"
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "MipsTargetMachine.h"
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#include "MipsMachineFunction.h"
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#include "MipsMachineFunction.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/Instructions.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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@ -75,6 +77,7 @@ namespace {
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}
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}
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virtual void EmitFunctionBodyStart();
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virtual void EmitFunctionBodyStart();
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virtual void EmitFunctionBodyEnd();
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virtual void EmitFunctionBodyEnd();
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virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
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static const char *getRegisterName(unsigned RegNo);
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static const char *getRegisterName(unsigned RegNo);
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virtual void EmitFunctionEntryLabel();
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virtual void EmitFunctionEntryLabel();
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@ -227,6 +230,23 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() {
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}
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}
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/// isBlockOnlyReachableByFallthough - Return true if the basic block has
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/// exactly one predecessor and the control transfer mechanism between
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/// the predecessor and this block is a fall-through.
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bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
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const {
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// The predecessor has to be immediately before this block.
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const MachineBasicBlock *Pred = *MBB->pred_begin();
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// If the predecessor is a switch statement, assume a jump table
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// implementation, so it is not a fall through.
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if (const BasicBlock *bb = Pred->getBasicBlock())
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if (isa<SwitchInst>(bb->getTerminator()))
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return false;
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return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
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}
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// Print out an operand for an inline asm expression.
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// Print out an operand for an inline asm expression.
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bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant,const char *ExtraCode,
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unsigned AsmVariant,const char *ExtraCode,
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@ -542,7 +542,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
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SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
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SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
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if (IsPIC) {
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if (!IsPIC) {
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SDValue Ops[] = { JTI };
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SDValue Ops[] = { JTI };
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HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
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HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
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} else // Emit Load from Global Pointer
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} else // Emit Load from Global Pointer
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@ -0,0 +1,33 @@
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; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s
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define i32 @main() nounwind readnone {
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entry:
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%x = alloca i32, align 4 ; <i32*> [#uses=2]
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volatile store i32 2, i32* %x, align 4
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%0 = volatile load i32* %x, align 4 ; <i32> [#uses=1]
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; CHECK: lui $3, %hi($JTI0_0)
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; CHECK: sll $2, $2, 2
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; CHECK: addiu $3, $3, %lo($JTI0_0)
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switch i32 %0, label %bb4 [
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i32 0, label %bb5
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i32 1, label %bb1
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i32 2, label %bb2
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i32 3, label %bb3
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]
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bb1: ; preds = %entry
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ret i32 2
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; CHECK: $BB0_2
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bb2: ; preds = %entry
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ret i32 0
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bb3: ; preds = %entry
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ret i32 3
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bb4: ; preds = %entry
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ret i32 4
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bb5: ; preds = %entry
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ret i32 1
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}
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