forked from OSchip/llvm-project
[RISCV] Extend RVV VType info with the type's AVL (NFC)
This patch factors out the "VLMax" operand passed to most scalable-vector ISel patterns into a property of each VType. This is seen as a preparatory change to allow RVV in the future to more easily support fixed-length vector types with constrained vector lengths, with the AVL operand set to the length of the fixed-length vector. It has no effect on the scalable code generation path. Reviewed By: HsiangKai Differential Revision: https://reviews.llvm.org/D94594
This commit is contained in:
Fraser Cormack
parent
f373b30923
commit
15fd6bae0e
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@ -137,6 +137,9 @@ class VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M,
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LMULInfo LMul = M;
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ValueType Scalar = Scal;
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RegisterClass ScalarRegClass = ScalarReg;
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// The pattern fragment which produces the AVL operand, representing the
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// "natural" vector length for this type. For scalable vectors this is VLMax.
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OutPatFrag AVL = VLMax;
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}
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class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew,
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@ -234,6 +237,10 @@ class MTypeInfo<ValueType Mas, LMULInfo M, string Bx> {
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int SEW = 8;
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LMULInfo LMul = M;
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string BX = Bx; // Appendix of mask operations.
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// The pattern fragment which produces the AVL operand, representing the
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// "natural" vector length for this mask type. For scalable masks this is
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// VLMax.
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OutPatFrag AVL = VLMax;
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}
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defset list<MTypeInfo> AllMasks = {
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@ -47,6 +47,7 @@ multiclass VPatUSLoadStoreSDNode<LLVMType type,
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LLVMType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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RegisterClass reg_rs1,
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VReg reg_class>
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{
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@ -54,16 +55,16 @@ multiclass VPatUSLoadStoreSDNode<LLVMType type,
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defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
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// Load
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def : Pat<(type (load reg_rs1:$rs1)),
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(load_instr reg_rs1:$rs1, VLMax, sew)>;
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(load_instr reg_rs1:$rs1, avl, sew)>;
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// Store
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def : Pat<(store type:$rs2, reg_rs1:$rs1),
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(store_instr reg_class:$rs2, reg_rs1:$rs1, VLMax, sew)>;
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(store_instr reg_class:$rs2, reg_rs1:$rs1, avl, sew)>;
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}
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multiclass VPatUSLoadStoreSDNodes<RegisterClass reg_rs1> {
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foreach vti = AllVectors in
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defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.Mask, vti.SEW, vti.LMul,
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reg_rs1, vti.RegClass>;
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vti.AVL, reg_rs1, vti.RegClass>;
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}
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class VPatBinarySDNode_VV<SDNode vop,
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@ -73,6 +74,7 @@ class VPatBinarySDNode_VV<SDNode vop,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg RetClass,
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VReg op_reg_class> :
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Pat<(result_type (vop
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@ -81,7 +83,7 @@ class VPatBinarySDNode_VV<SDNode vop,
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(!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
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op_reg_class:$rs1,
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op_reg_class:$rs2,
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VLMax, sew)>;
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avl, sew)>;
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class VPatBinarySDNode_XI<SDNode vop,
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string instruction_name,
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@ -92,6 +94,7 @@ class VPatBinarySDNode_XI<SDNode vop,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg RetClass,
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VReg vop_reg_class,
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ComplexPattern SplatPatKind,
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@ -102,17 +105,17 @@ class VPatBinarySDNode_XI<SDNode vop,
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(!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX)
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vop_reg_class:$rs1,
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xop_kind:$rs2,
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VLMax, sew)>;
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avl, sew)>;
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multiclass VPatBinarySDNode_VV_VX<SDNode vop, string instruction_name>
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{
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foreach vti = AllIntegerVectors in {
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def : VPatBinarySDNode_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass>;
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
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def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
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vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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SplatPat, GPR>;
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}
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}
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@ -123,14 +126,14 @@ multiclass VPatBinarySDNode_VV_VX_VI<SDNode vop, string instruction_name,
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foreach vti = AllIntegerVectors in {
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def : VPatBinarySDNode_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass>;
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
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def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
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vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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SplatPat, GPR>;
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def : VPatBinarySDNode_XI<vop, instruction_name, "VI",
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vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass,
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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!cast<ComplexPattern>(SplatPat#_#ImmType),
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ImmType>;
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}
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@ -144,6 +147,7 @@ class VPatBinarySDNode_VF<SDNode vop,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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OutPatFrag avl,
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VReg RetClass,
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VReg vop_reg_class,
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DAGOperand xop_kind> :
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@ -152,16 +156,16 @@ class VPatBinarySDNode_VF<SDNode vop,
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(!cast<Instruction>(instruction_name#"_VF_"#vlmul.MX)
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vop_reg_class:$rs1,
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ToFPR32<xop_type, xop_kind, "rs2">.ret,
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VLMax, sew)>;
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avl, sew)>;
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multiclass VPatBinaryFPSDNode_VV_VF<SDNode vop, string instruction_name> {
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foreach vti = AllFloatVectors in {
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def : VPatBinarySDNode_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass>;
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vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
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def : VPatBinarySDNode_VF<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
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vti.SEW, vti.LMul, vti.RegClass, vti.RegClass,
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vti.SEW, vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
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vti.ScalarRegClass>;
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}
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}
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@ -173,7 +177,7 @@ multiclass VPatBinaryFPSDNode_R_VF<SDNode vop, string instruction_name> {
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(!cast<Instruction>(instruction_name#"_VF_"#fvti.LMul.MX)
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fvti.RegClass:$rs1,
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ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret,
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VLMax, fvti.SEW)>;
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fvti.AVL, fvti.SEW)>;
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}
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multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
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@ -186,7 +190,7 @@ multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
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SwapHelper<(instruction),
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(instruction vti.RegClass:$rs1),
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(instruction vti.RegClass:$rs2),
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(instruction VLMax, vti.SEW),
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(instruction vti.AVL, vti.SEW),
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swap>.Value>;
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}
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}
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@ -204,7 +208,7 @@ multiclass VPatIntegerSetCCSDNode_XI<CondCode cc,
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SwapHelper<(instruction),
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(instruction vti.RegClass:$rs1),
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(instruction xop_kind:$rs2),
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(instruction VLMax, vti.SEW),
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(instruction vti.AVL, vti.SEW),
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swap>.Value>;
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}
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}
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@ -242,7 +246,7 @@ multiclass VPatFPSetCCSDNode_VV<CondCode cc, string instruction_name> {
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(fvti.Vector fvti.RegClass:$rs2),
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cc)),
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(!cast<Instruction>(instruction_name#"_VV_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, fvti.RegClass:$rs2, VLMax, fvti.SEW)>;
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fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.AVL, fvti.SEW)>;
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}
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multiclass VPatFPSetCCSDNode_VF<CondCode cc, string instruction_name> {
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@ -253,7 +257,7 @@ multiclass VPatFPSetCCSDNode_VF<CondCode cc, string instruction_name> {
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(!cast<Instruction>(instruction_name#"_VF_"#fvti.LMul.MX)
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fvti.RegClass:$rs1,
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ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret,
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VLMax, fvti.SEW)>;
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fvti.AVL, fvti.SEW)>;
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}
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multiclass VPatFPSetCCSDNode_FV<CondCode cc, string swapped_op_instruction_name> {
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@ -264,7 +268,7 @@ multiclass VPatFPSetCCSDNode_FV<CondCode cc, string swapped_op_instruction_name>
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(!cast<Instruction>(swapped_op_instruction_name#"_VF_"#fvti.LMul.MX)
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fvti.RegClass:$rs1,
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ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret,
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VLMax, fvti.SEW)>;
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fvti.AVL, fvti.SEW)>;
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}
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multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc,
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@ -283,7 +287,7 @@ multiclass VPatExtendSDNode_V<list<SDNode> ops, string inst_name, string suffix,
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foreach op = ops in
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def : Pat<(vti.Vector (op (fti.Vector fti.RegClass:$rs2))),
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(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
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fti.RegClass:$rs2, VLMax, vti.SEW)>;
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fti.RegClass:$rs2, fti.AVL, vti.SEW)>;
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}
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}
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@ -306,11 +310,11 @@ foreach vti = AllIntegerVectors in {
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def : Pat<(sub (vti.Vector (SplatPat XLenVT:$rs2)),
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(vti.Vector vti.RegClass:$rs1)),
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(!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
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vti.RegClass:$rs1, GPR:$rs2, VLMax, vti.SEW)>;
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vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.SEW)>;
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def : Pat<(sub (vti.Vector (SplatPat_simm5 XLenVT:$rs2)),
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(vti.Vector vti.RegClass:$rs1)),
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(!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX)
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vti.RegClass:$rs1, simm5:$rs2, VLMax, vti.SEW)>;
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vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.SEW)>;
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}
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// 12.3. Vector Integer Extension
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@ -343,7 +347,7 @@ foreach vtiTofti = AllFractionableVF2IntVectors in {
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defvar fti = vtiTofti.Fti;
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def : Pat<(fti.Vector (riscv_trunc_vector (vti.Vector vti.RegClass:$rs1))),
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(!cast<Instruction>("PseudoVNSRL_WI_"#fti.LMul.MX)
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vti.RegClass:$rs1, 0, VLMax, fti.SEW)>;
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vti.RegClass:$rs1, 0, fti.AVL, fti.SEW)>;
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}
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// 12.8. Vector Integer Comparison Instructions
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@ -390,47 +394,48 @@ foreach vti = AllIntegerVectors in {
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def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), vti.RegClass:$rs1,
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vti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX)
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vti.RegClass:$rs2, vti.RegClass:$rs1, VMV0:$vm, VLMax, vti.SEW)>;
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vti.RegClass:$rs2, vti.RegClass:$rs1, VMV0:$vm,
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vti.AVL, vti.SEW)>;
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def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat XLenVT:$rs1),
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vti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX)
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vti.RegClass:$rs2, GPR:$rs1, VMV0:$vm, VLMax, vti.SEW)>;
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vti.RegClass:$rs2, GPR:$rs1, VMV0:$vm, vti.AVL, vti.SEW)>;
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def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat_simm5 simm5:$rs1),
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vti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX)
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vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, VLMax, vti.SEW)>;
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vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, vti.AVL, vti.SEW)>;
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}
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// 16.1. Vector Mask-Register Logical Instructions
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foreach mti = AllMasks in {
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def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)),
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(!cast<Instruction>("PseudoVMAND_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
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VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
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def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)),
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(!cast<Instruction>("PseudoVMOR_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
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VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
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def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)),
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(!cast<Instruction>("PseudoVMXOR_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
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VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
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def : Pat<(mti.Mask (vnot (and VR:$rs1, VR:$rs2))),
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(!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
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VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
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def : Pat<(mti.Mask (vnot (or VR:$rs1, VR:$rs2))),
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(!cast<Instruction>("PseudoVMNOR_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
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VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
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def : Pat<(mti.Mask (vnot (xor VR:$rs1, VR:$rs2))),
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(!cast<Instruction>("PseudoVMXNOR_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
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VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
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def : Pat<(mti.Mask (and VR:$rs1, (vnot VR:$rs2))),
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(!cast<Instruction>("PseudoVMANDNOT_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
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VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
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def : Pat<(mti.Mask (or VR:$rs1, (vnot VR:$rs2))),
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(!cast<Instruction>("PseudoVMORNOT_MM_"#mti.LMul.MX)
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VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
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VR:$rs1, VR:$rs2, mti.AVL, mti.SEW)>;
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}
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} // Predicates = [HasStdExtV]
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@ -468,7 +473,7 @@ foreach fvti = AllFloatVectors in {
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fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX)
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fvti.RegClass:$rs2, fvti.RegClass:$rs1, VMV0:$vm,
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VLMax, fvti.SEW)>;
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fvti.AVL, fvti.SEW)>;
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def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
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(splat_vector fvti.ScalarRegClass:$rs1),
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@ -476,13 +481,13 @@ foreach fvti = AllFloatVectors in {
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(!cast<Instruction>("PseudoVFMERGE_VFM_"#fvti.LMul.MX)
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fvti.RegClass:$rs2,
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ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret,
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VMV0:$vm, VLMax, fvti.SEW)>;
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VMV0:$vm, fvti.AVL, fvti.SEW)>;
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def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
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(splat_vector (fvti.Scalar fpimm0)),
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fvti.RegClass:$rs2)),
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(!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
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fvti.RegClass:$rs2, 0, VMV0:$vm, VLMax, fvti.SEW)>;
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fvti.RegClass:$rs2, 0, VMV0:$vm, fvti.AVL, fvti.SEW)>;
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}
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} // Predicates = [HasStdExtV, HasStdExtF]
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@ -494,17 +499,17 @@ let Predicates = [HasStdExtV] in {
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foreach vti = AllIntegerVectors in {
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def : Pat<(vti.Vector (splat_vector GPR:$rs1)),
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(!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
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GPR:$rs1, VLMax, vti.SEW)>;
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GPR:$rs1, vti.AVL, vti.SEW)>;
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def : Pat<(vti.Vector (splat_vector simm5:$rs1)),
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(!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
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simm5:$rs1, VLMax, vti.SEW)>;
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simm5:$rs1, vti.AVL, vti.SEW)>;
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}
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foreach mti = AllMasks in {
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def : Pat<(mti.Mask immAllOnesV),
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(!cast<Instruction>("PseudoVMSET_M_"#mti.BX) VLMax, mti.SEW)>;
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(!cast<Instruction>("PseudoVMSET_M_"#mti.BX) mti.AVL, mti.SEW)>;
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def : Pat<(mti.Mask immAllZerosV),
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(!cast<Instruction>("PseudoVMCLR_M_"#mti.BX) VLMax, mti.SEW)>;
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(!cast<Instruction>("PseudoVMCLR_M_"#mti.BX) mti.AVL, mti.SEW)>;
|
||||
}
|
||||
} // Predicates = [HasStdExtV]
|
||||
|
||||
|
|
@ -513,10 +518,10 @@ foreach vti = AllIntegerVectors in {
|
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if !eq(vti.SEW, 64) then {
|
||||
def : Pat<(vti.Vector (rv32_splat_i64 GPR:$rs1)),
|
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(!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
|
||||
GPR:$rs1, VLMax, vti.SEW)>;
|
||||
GPR:$rs1, vti.AVL, vti.SEW)>;
|
||||
def : Pat<(vti.Vector (rv32_splat_i64 simm5:$rs1)),
|
||||
(!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
|
||||
simm5:$rs1, VLMax, vti.SEW)>;
|
||||
simm5:$rs1, vti.AVL, vti.SEW)>;
|
||||
}
|
||||
}
|
||||
} // Predicates = [HasStdExtV, IsRV32]
|
||||
|
|
@ -526,10 +531,10 @@ foreach fvti = AllFloatVectors in {
|
|||
def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)),
|
||||
(!cast<Instruction>("PseudoVFMV_V_F_"#fvti.LMul.MX)
|
||||
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret,
|
||||
VLMax, fvti.SEW)>;
|
||||
fvti.AVL, fvti.SEW)>;
|
||||
|
||||
def : Pat<(fvti.Vector (splat_vector (fvti.Scalar fpimm0))),
|
||||
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
|
||||
0, VLMax, fvti.SEW)>;
|
||||
0, fvti.AVL, fvti.SEW)>;
|
||||
}
|
||||
} // Predicates = [HasStdExtV, HasStdExtF]
|
||||
|
|
|
|||
Loading…
Reference in New Issue